Semiconductor memory device, and semiconductor package and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2025056799-A1
Application number	US-202418596764-A
Country	US
Kind code	A1
Filing date	Mar 6, 2024
Priority date	Aug 7, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions; a peripheral circuit structure on the substrate and including peripheral circuits; a cell array structure on the peripheral circuit structure; a first through-via extending into the substrate in the mat separation region; and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via in a plan view.

2 . The semiconductor memory device of claim 1 , wherein the cell array structure comprises:
a plurality of memory blocks on at least one of the mat regions; and a dummy block on the mat separation region, wherein the second through-via extends into the dummy block.

3 . The semiconductor memory device of claim 2 , wherein the dummy block comprises:
inter-electrode insulating layers that are sequentially stacked; and dummy electrode layers respectively between the inter-electrode insulating layers, wherein each of the dummy electrode layers comprises: a first dummy electrode and a second dummy electrode spaced apart from each other; and a mold insulating layer between the first dummy electrode and the second dummy electrode, and wherein the second through-via extends into the mold insulating layer and the inter-electrode insulating layers.

4 . The semiconductor memory device of claim 1 , wherein the mat regions include first and second mat regions arranged in a first direction,
wherein the peripheral circuit structure comprises: a first page buffer region on the first mat region and adjacent to the second mat region; and a second page buffer region on the second mat region and adjacent to the first mat region, and wherein the mat separation region is between the first page buffer region and the second page buffer region.

5 . The semiconductor memory device of claim 4 , wherein the first mat region includes a first sub-mat region and a second sub-mat region that are adjacent to each other in a second direction intersecting the first direction,
wherein the peripheral circuit structure comprises: a first decoder region on the first sub-mat region and adjacent to the second sub-mat region; and a second decoder region on the second sub-mat region and adjacent to the first sub-mat region, wherein the cell array structure comprises: first blocks on the first sub-mat region and spaced apart from each other in the first direction; and second blocks on the second sub-mat region and spaced apart from each other in the first direction, wherein end portions of the first blocks have a stepped profile on the first decoder region, and wherein end portions of the second blocks have a stepped profile on the second decoder region.

6 . The semiconductor memory device of claim 4 , wherein the peripheral circuit structure comprises:
a first decoder region on a center portion of the first mat region; and a second decoder region on a center portion of the second mat region, wherein the cell array structure comprises: first blocks on the first mat region and spaced apart from each other in the first direction; and second blocks on the second mat region and spaced apart from each other in the first direction, wherein respective center portions of the first blocks overlap the first decoder region, wherein respective center portions of the second blocks overlap the second decoder region, wherein each of the first blocks includes alternately stacked first electrode layers and first inter-electrode insulating layers, and wherein each of the first electrode layers includes a pad portion and a pad connection portion on the first decoder region.

7 . The semiconductor memory device of claim 1 , wherein the mat regions include first and second mat regions arranged in a first direction,
wherein the first mat region includes a first sub-mat region and a second sub-mat region that are adjacent to each other in a second direction intersecting the first direction, and wherein the peripheral circuit structure comprises: a first page buffer region on the first sub-mat region and adjacent to the mat separation region; and a second page buffer region on the second sub-mat region and adjacent to a sidewall of the substrate.

8 . The semiconductor memory device of claim 1 , further comprising:
a first input/output pad on a lower surface of the substrate and electrically connected to the first through-via; and a second input/output pad on an upper portion of the cell array structure and electrically connected to the second through-via, wherein a width of the first input/output pad is different from a width of the second input/output pad.

9 . The semiconductor memory device of claim 1 , wherein the peripheral circuit structure comprises:
transistors on the substrate; a first interlayer insulating layer on the transistors; a first etch stop layer on the first interlayer insulating layer; a second interlayer insulating layer on the first etch stop layer; a second etch stop layer on the second interlayer insulating layer; and a mat separation insulating layer extending into the second etch stop layer, the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer on the mat separation region and adjacent to the substrate, and wherein the first through-via extends into the mat separation insulating layer.

10 . The semiconductor memory device of claim 9 , wherein the peripheral circuit structure further comprises:
a first peripheral interconnection line on the first etch stop layer; and a second peripheral interconnection line on the second etch stop layer, and wherein the second through-via is in contact with the second peripheral interconnection line.

11 . A semiconductor package comprising:
a package substrate; semiconductor dies sequentially stacked on the package substrate; and a mold layer on side surfaces of the semiconductor dies and an upper surface of the package substrate, wherein each of the semiconductor dies comprises: a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions; a peripheral circuit structure on the substrate and including peripheral circuits; a cell array structure on the peripheral circuit structure; a first through-via extending into the substrate in the mat separation region; a first input/output pad on a lower surface of the first through-via; a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via; and a second input/output pad on the second through-via, wherein the second through-via overlaps the first through-via, wherein the second input/output pad of a first one of the semiconductor dies is in contact with the first input/output pad of a second one of the semiconductor dies, and wherein the second one of the semiconductor dies is on the first one of the semiconductor dies.

12 . The semiconductor package of claim 11 , wherein the cell array structure comprises:
a plurality of memory blocks on at least one of the mat regions; and a dummy block on the mat separation region, and wherein the second through-via extends into the dummy block.

13 . The semiconductor package of claim 12 , wherein the dummy block comprises:
inter-electrode insulating layers that are sequentially stacked; and dummy electrode layers respectively between the inter-el

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Kumhyo
• Kim Hongsoo
• Lee Jeon Il
• Choi Hyun-Mook

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title