Managing three-dimensional semiconductive devices

Patent metadata

Field	Value
Publication number	US-2025056793-A1
Application number	US-202318477512-A
Country	US
Kind code	A1
Filing date	Sep 28, 2023
Priority date	Aug 11, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

Systems, devices, and methods for managing three-dimensional semiconductor devices are provided. In one aspect, a method includes: forming strings of memory cells in a first side of a semiconductor substrate having a semiconductor material, forming alternating stripes of the semiconductor material and an isolating material in a second, opposite side of the semiconductor substrate, and forming bit lines in the second side of the semiconductor substrate. The bit lines can be formed by depositing a layer of a metallic material on the alternating stripes of the semiconductor material and the isolating material, and forming each bit line of the bit lines in a corresponding stripe of the semiconductor material of the alternating stripes by forming a composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material.

First claim

1 . A method comprising:
forming a plurality of strings of memory cells in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; forming a plurality of alternating stripes of the semiconductor material and an isolating material in a second side of the semiconductor substrate along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side along the vertical direction; and forming a plurality of bit lines in the second side of the semiconductor substrate, wherein forming the plurality of bit lines comprises:
depositing a layer of a metallic material on the plurality of alternating stripes of the semiconductor material and the isolating material; and
forming each bit line of the plurality of bit lines in a corresponding stripe of the semiconductor material of the plurality of alternating stripes by forming a composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material.

2 . The method of claim 1 , wherein forming the composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material comprises:
annealing the metallic material and the semiconductor material, such that the metallic material reacts with the semiconductor material to form the composite conductive material.

3 . The method of claim 1 , wherein the semiconductor material comprises silicon, the isolating material comprises oxide, and the composite conductive material comprises silicide.

4 . The method of claim 1 , further comprising:
after forming the plurality of bit lines in the second side of the semiconductor substrate, removing a residue of the metallic material from the second side of the semiconductor substrate.

5 . The method of claim 1 , wherein forming the plurality of alternating stripes of the semiconductor material and the isolating material in the second side of the semiconductor substrate comprises:
thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the plurality of alternating stripes of the semiconductor material and the isolating material, wherein the method further comprises:
implanting ions into the second side of the semiconductor substrate, and
wherein forming the composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material comprises:
forming the composite conductive material based on the metallic material and the semiconductor material with the implanted ions.

6 . The method of claim 5 , wherein implanting the ions into the second side of the semiconductor substrate comprises:
implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions under an activation temperature.

7 . The method of claim 6 , wherein the semiconductor material comprises silicon, the semiconductor ions comprise Germanium (Ge) ions, and the N+ type ions comprise arsenic (As) ions or phosphorus (P) ions.

8 . The method of claim 6 , wherein the activation temperature is lower than a nominal temperature for activating the N+ type ions without implanting the semiconductor ions.

9 . The method of claim 5 , wherein thinning the semiconductor substrate from the second side of the semiconductor substrate comprises:
etching the semiconductor material in the second side of the semiconductor substrate; and polishing a top surface of the etched semiconductor material in the second side of the semiconductor substrate.

10 . The method of claim 5 , wherein each memory cell of the plurality of strings of memory cells comprises a vertical transistor along the vertical direction, and
wherein forming the plurality of strings of memory cells comprises:
forming a gate terminal of the vertical transistor by depositing at least one metallic layer on an inner surface of a trench along the vertical direction;
forming a first terminal of the vertical transistor by implanting the ions from the first side of the semiconductor substrate; and
forming a second terminal of the vertical transistor by implanting the ions into the second side of the semiconductor substrate.

11 . The method of claim 10 , wherein each of the plurality of bit lines is formed on the second terminal of the vertical transistor and is coupled to the second terminal of the vertical transistor.

12 . The method of claim 10 , wherein each memory cell of the plurality of strings of memory cells further comprises a capacitor coupled to the vertical transistor, and
wherein forming the plurality of strings of memory cells comprises:
forming the capacitor before forming the vertical transistor, the capacitor being over the vertical transistor along the vertical direction.

13 . The method of claim 10 , wherein forming the plurality of strings of memory cells comprises:
forming gate terminals of a pair of independent vertical transistors in a same trench along the vertical direction, the gate terminals being separated by an isolating material along a third direction perpendicular to the vertical direction and the horizontal direction.

14 . The method of claim 13 , further comprising:
forming an isolating region between adjacent pairs of independent vertical transistors along the third direction.

15 . The method of claim 1 , wherein the plurality of strings of memory cells and the plurality of bit lines are formed in an array die, and
wherein the method further comprises:
integrating a control die with the array die by bonding the first side of the semiconductor substrate with a front side of the control die and conductively coupling one or more conductive lines of the array die to a control circuit in the front side of the control die.

16 . A semiconductor device, comprising:
a plurality of strings of memory cells in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; and a plurality of bit lines in a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines are separated by an isolating material along a horizontal direction perpendicular to the vertical direction, wherein the plurality of bit lines are made of a composite conductive material that is based on the semiconductor material, and wherein the plurality of bit lines are on a layer of the semiconductor material with implanted ions.

17 . The semiconductor device of claim 16 , wherein the implanted ions comprise semiconductor ions and N+ type ions.

18 . The semiconductor device of claim 16 , wherein each memory cell of the plurality of strings of memory cells comprises a vertical transistor along the vertical direction, and
wherein a portion of the layer of the semiconductor material with the implanted ions is configured to be a terminal of the vertical transistor and to be conductively coupled to a corresponding bit line.

19 . The semiconductor device of claim 18 , wherein gate terminals of a pair of independent vertical transistors are in a same trench along the vertical direction and separated by an isolating materi

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Tang Zhaoyun
• Lan Tian
• Hua Wenyu

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/482 Primary

  Bit lines · CPC title