Fin field-effect transistor device with hybrid conduction mechanism

Patent metadata

Field	Value
Publication number	US-2025040196-A1
Application number	US-202218552180-A
Country	US
Kind code	A1
Filing date	Dec 30, 2022
Priority date	Dec 30, 2022
Publication date	Jan 30, 2025
Grant date	—

Abstract

A fin field-effect transistor device with hybrid conduction mechanism, including a fin field-effect transistor, a second source region, and a second drain region; the fin field-effect transistor includes a substrate, a fin channel region, a first source region, and a first drain region; the height of the second source region is not lower than the height of the substrate between the first source region and the first drain region; the first source region, the first drain region and the second drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, the second source region is doped with second ions. This scheme can realize hybrid conduction of fin channel diffusion drift current and bottom channel band-to-band tunneling current, thus obtaining better ultra-steep switching characteristics.

First claim

1 . A fin field-effect transistor device with hybrid conduction mechanism, including:
a fin field-effect transistor, which includes a substrate, a fin channel region, a first source region and a first drain region; the first source region and the first drain region are arranged along a first direction above the substrate; the fin channel regionis formed on the substrate between the first source region and the first drain region; wherein, the first source region and the first drain region are doped with first ions; wherein, the first direction represents the channel direction of the fin field-effect transistor; a second source region and a second drain region, the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region; the height of the second source region and the height of the second drain region are not lower than the height of the substrate between the first source region and the first drain region; wherein, the second drain region is doped with the first ions, the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

2 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the thickness of the second source region and/or the second drain region is 5 nm-50 nm.

3 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the first ions are P-type ions or N-type ions.

4 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the second ions are P-type ions or N-type ions.

5 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the ion concentration doped in the second source region and/or the second drain region is 1E16 cm −3 -1E22 cm −3 .

6 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the material of the second source region and the material of the second drain region are binary or ternary compounds of group II-VI, group III-V, or group IV-IV.

7 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 6 , wherein the material of the second source region and the material of the second drain region are Si, SiGe or Ge.

8 . The fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , wherein the fin field-effect transistor further includes:
a gate dielectric layer and a control gate, the gate dielectric layer wraps part of the surface of the channel layer, and wraps the substrate between the first source region and the first drain region; the control gate wraps the surface of the gate dielectric layer; a sidewall, formed on both sides of the gate dielectric layer and the control gate along the first direction; a source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and fully wrapped the first source region and the second source region, and the first drain region and the second source region, respectively; the gate metal layer is formed at the top of the control gate; a interlayer dielectric layer, covering the surfaces of the source metal layer, the gate metal layer, the drain metal layer, and the sidewall; a metal contact layer, penetrating the interlayer dielectric layer, and is respectively connected to the source metal layer, the gate metal layer, and the drain metal layer.

9 . A method for manufacturing a fin field-effect transistor device with hybrid conduction mechanism, which is used for manufacturing the fin field-effect transistor device with hybrid conduction mechanism according to claim 1 , the method includes:
forming the fin field-effect transistor, the second source region, and the second drain region; wherein, the fin field-effect transistor includes the substrate, the fin channel region, the first source region and the first drain region; the first source region and the first drain region are arranged along the first direction above the substrate; the fin channel region is formed on the substrate between the first source region and the first drain region; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, wherein, the first source region, the first drain region, and the second drain region are doped with the first ions; the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

10 . The method for manufacturing a fin field-effect transistor device with hybrid conduction mechanism according to claim 9 , wherein the forming the fin field-effect transistor, the second source region and the second drain region, specifically includes:
providing the substrate; forming a dummy gate structure and the sidewall; the dummy gate structure straddles the substrate; the sidewall are closely attached to the two sides of the dummy gate structure along the first direction; etching the substrate on both sides of the sidewall along the first direction to form the fin channel region, and over-etching the substrate on both sides of the sidewall along the first direction to form a first cavity and a second cavity; wherein, the dummy gate structure and the sidewall wrap the fin channel region; the first cavity and the second cavity are arranged in sequence along the first direction; forming the second source region and the second drain region; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity; forming the first source region and the first drain region; the first source region and the first drain region are respectively formed at the top ends of the second source region and the second drain region; removing the dummy gate structure; forming the gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer, and the metal contact layer.

11 . The method for manufacturing a fin field-effect transistor device with hybrid conduction mechanism according to claim 10 , wherein the forming the second source region and the second drain region, specifically includes:
forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure, and the surface of the sidewall; filling the material of the second source region in the first cavity to form the second source region, and then removing the patterned first mask layer; forming a patterned second mask layer; the patterned second mask layer covers the second source region, the dummy gate structure, and the surface of the sidewall; filling the material of the second drain region in the second cavity to form the second drain region, and then removing the patterned second mask layer.

12 . An electronic device, comprising the fin field-effect transistor device with hybrid conduction mechanism according to claim 1 .

13 . (canceled)

14 . The method for manufacturing a fin field-effect transistor device with hybrid conduction mechanism according to claim 9 , wherein the thickness of the second source region and/or the second drain region is 5 nm-50 nm.

15 . The method for manufacturing a fin field-effect transistor device with hybrid conduct

Assignees

• Univ Fudan
• Shanghai Integrated Circuit Mfg Innovation Center Co Ltd

Inventors

• Wu Chunlei
• Xu Yumin
• Shen Boqian
• Zhao Fei
• Yang Zichen
• Zhang Wei
• Xu Min

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D12/021

  of gated diodes, e.g. field-controlled diodes [FCD] · CPC title