Contact resistance test structure for stacked fets

Patent metadata

Field	Value
Publication number	US-2024426895-A1
Application number	US-202318341003-A
Country	US
Kind code	A1
Filing date	Jun 26, 2023
Priority date	Jun 26, 2023
Publication date	Dec 26, 2024
Grant date	—

Abstract

A semiconductor test structure includes a first transistor active area comprising at least a first source/drain region, and a second transistor active area stacked on the first transistor active area and comprising at least a second source/drain region. At least one dielectric layer is disposed between the first transistor active area and the second transistor active area. The semiconductor test structure further includes a plurality of contact structures spaced apart from each other and disposed on the second source/drain region, and at least one gate structure extending across the first transistor active area and the second transistor active area. Contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region, and the second source/drain region is continuous between the plurality of contact structures.

First claim

What is claimed is:

1 . A semiconductor test structure, comprising:
a first transistor active area comprising at least a first source/drain region; a second transistor active area stacked on the first transistor active area and comprising at least a second source/drain region; at least one dielectric layer disposed between the first transistor active area and the second transistor active area; a plurality of contact structures spaced apart from each other and disposed on the second source/drain region; and at least one gate structure extending across the first transistor active area and the second transistor active area; wherein contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region; and wherein the second source/drain region is continuous between the plurality of contact structures.

2 . The semiconductor test structure of claim 1 , wherein a size of the first transistor active area is equal to a size of the second transistor active area.

3 . The semiconductor test structure of claim 1 , wherein the plurality of contact structures are spaced apart from each other at different distances.

4 . The semiconductor test structure of claim 1 , wherein the first source/drain region has a different doping type than the second source/drain region.

5 . The semiconductor test structure of claim 1 , wherein:
the first transistor active area comprises a first stacked structure, wherein the first stacked structure comprises a first plurality of gate structures alternately stacked with a first plurality of channel layers; and the second transistor active area comprises a second stacked structure, wherein the second stacked structure comprises a second plurality of gate structures alternately stacked with a second plurality of channel layers.

6 . The semiconductor test structure of claim 5 , wherein:
the first transistor active area comprises a first plurality of source/drain regions disposed on sides of the first stacked structure; and the second transistor active area comprises a second plurality of source/drain regions disposed on sides of the second stacked structure.

7 . The semiconductor test structure of claim 5 , wherein:
the first transistor active area comprises a first plurality of sacrificial semiconductor layers alternately stacked with the first plurality of channel layers, wherein respective ones of the first plurality of sacrificial semiconductor layers are disposed adjacent to respective ones of the first plurality of gate structures; and the second transistor active area comprises a second plurality of sacrificial semiconductor layers alternately stacked with the second plurality of channel layers, wherein respective ones of the second plurality of sacrificial semiconductor layers are disposed adjacent to respective ones of the second plurality of gate structures.

8 . The semiconductor test structure of claim 1 , wherein the semiconductor test structure lacks shallow trench isolation regions.

9 . The semiconductor test structure of claim 1 , wherein at least the second transistor active area comprises a plurality of transistors without isolation regions between the plurality of transistors.

10 . The semiconductor test structure of claim 1 , wherein:
the plurality of contact structures are connected to respective ones of a plurality of conductive portions through respective ones of a plurality of vias; and the respective ones of the plurality of conductive portions are isolated from each other.

11 . The semiconductor test structure of claim 1 , further comprising a plurality of barrier layers between the plurality of contact structures and the second source/drain region, wherein the contact resistance is measured at respective ones of the plurality of barrier layers.

12 . A semiconductor test structure, comprising:
a first active area comprising at least a first nanosheet transistor structure and a first source/drain region corresponding to the first nanosheet transistor structure, wherein the first nanosheet transistor structure comprises a first plurality of gate structures alternately stacked with a first plurality of channel layers; a second active area stacked on the first active area and comprising at least a second nanosheet transistor structure and a second source/drain region corresponding to the second nanosheet transistor structure, wherein the second nanosheet transistor structure comprises a second plurality of gate structures alternately stacked with a second plurality of channel layers; at least one dielectric layer disposed between the first active area and the second active area; and a plurality of contact structures spaced apart from each other and disposed on the second source/drain region; wherein contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region; and wherein the second source/drain region is continuous between the plurality of contact structures.

13 . The semiconductor test structure of claim 12 , wherein a size of the first active area is equal to a size of the second active area.

14 . The semiconductor test structure of claim 12 , wherein the plurality of contact structures are spaced apart from each other at different distances.

15 . The semiconductor test structure of claim 12 , wherein:
the first active area comprises a first plurality of sacrificial semiconductor layers alternately stacked with the first plurality of channel layers, wherein respective ones of the first plurality of sacrificial semiconductor layers are disposed adjacent to respective ones of the first plurality of gate structures; and the second active area comprises a second plurality of sacrificial semiconductor layers alternately stacked with the second plurality of channel layers, wherein respective ones of the second plurality of sacrificial semiconductor layers are disposed adjacent to respective ones of the second plurality of gate structures.

16 . The semiconductor test structure of claim 12 , wherein at least the second active area lacks shallow trench isolation regions.

17 . A semiconductor test structure, comprising:
a substrate; a first active area comprising a first source/drain region disposed on the substrate, the first source/drain region having a first doping type; a dielectric layer disposed on the first source/drain region; a second active area comprising a second source/drain region disposed on the dielectric layer, the second source/drain region having a second doping type different from the first doping type; a plurality of contact structures spaced apart from each other and disposed on the second source/drain region; and at least one gate structure extending across at least the second active area; wherein contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region; and wherein the second source/drain region is continuous between the plurality of contact structures.

18 . The semiconductor test structure of claim 17 , wherein an area of the first active area is equal to an area of the second active area.

19 . The semiconductor test structure of claim 17 , wherein the plurality of contact structures are spaced apart from each other at different distances.

20 . The semiconductor test structure of claim 17 , further comprising a plurality of barrier layers between the plurality of contact structures and the sec

Assignees

• IBM

Inventors

• Zhou Huimei
• Zhang Chen
• Wang Miaomiao
• Wang Junli

Classifications

• G01R27/205

  Measuring contact resistance of connections, e.g. of earth connections · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title