Stacked field effect transistors

Patent metadata

Field	Value
Publication number	US-2025311319-A1
Application number	US-202418617045-A
Country	US
Kind code	A1
Filing date	Mar 26, 2024
Priority date	Mar 26, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

A semiconductor device is provided that includes a multilayered insulator region located between stacked FETs. The multilayered insulator region is referred to herein as a multi-dielectric material middle isolation structure. The multi-dielectric material middle isolation structure includes a middle dielectric isolation structure having a middle dielectric isolation spacer located at two opposing ends of, or surrounding, the middle dielectric isolation structure. The middle dielectric isolation spacer protects the middle dielectric isolation structure during processing of the stacked FETs such that no damage to the middle dielectric isolation structure and the semiconductor channel regions of the stacked FETs is observed.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first field effect transistor (FET); a second FET stacked over the first FET; and a multi-dielectric material middle isolation structure located between the first FET and the second FET, wherein the multi-dielectric material middle isolation structure comprises a middle dielectric isolation structure having a first end and a second end opposite the first end, and a middle dielectric isolation spacer located at the first end and the second end of the middle dielectric isolation structure.

2 . The semiconductor device of claim 1 , wherein the middle dielectric isolation structure is composed of a first dielectric material, and the middle dielectric isolation spacer is composed of a second dielectric material that is compositionally different from the first dielectric material.

3 . The semiconductor device of claim 1 , further comprising a protective layer located on a topmost surface and a bottommost surface of the middle dielectric isolation spacer.

4 . The semiconductor device of claim 1 , wherein a semiconductor channel region of the first FET is spaced apart from a bottommost surface of the middle dielectric isolation spacer, and a semiconductor channel region of the second FET is spaced apart from a topmost surface of the middle dielectric isolation spacer.

5 . The semiconductor device of claim 4 , wherein the semiconductor channel region of the first FET comprises a plurality of vertical stacked and spaced apart first semiconductor channel material nanosheets and the semiconductor channel region of the second FET comprises a plurality of vertical stacked and spaced apart second semiconductor channel material nanosheets.

6 . The semiconductor device of claim 1 , wherein the first FET comprises a first gate structure wrapped around a plurality of vertical stacked and spaced apart first semiconductor channel material nanosheets, and first source/drain regions, and the second FET comprises a second gate structure wrapped around a plurality of vertical stacked and spaced apart second semiconductor channel material nanosheets, and second source/drain regions, wherein the first source/drain regions are spaced apart from the second source/drain regions by a frontside interlayer dielectric (ILD) layer.

7 . The semiconductor device of claim 1 , wherein the first FET is of a different conductivity type than the second FET.

8 . The semiconductor device of claim 1 , wherein the first FET and the second FET comprise a shared gate structure, and the shared gate structure directly contacts the middle dielectric isolation structure.

9 . The semiconductor device of claim 1 , wherein the first FET and the second FET comprise a shared gate structure, and the shared gate structure is isolated from each sidewall of the middle dielectric isolation structure by another middle dielectric isolation spacer.

10 . The semiconductor device of claim 1 , further comprising a frontside back-end-of-the-line (BEOL) structure located above the second FET, and a backside interconnect structure located beneath the first FET.

11 . The semiconductor device of claim 10 , wherein the backside interconnect structure is electrically connected to a first source/drain region of the first FET and the frontside BEOL structure is electrically connected to a source/drain region of the second FET.

12 . The semiconductor device of claim 11 , wherein another first source/drain region of the first FET is electrically connected to the frontside BEOL structure.

13 . The semiconductor device of claim 1 , wherein the middle dielectric isolation spacer has an inner sidewall in direct physical contact with the middle dielectric isolation structure and an outer sidewall that is vertically aligned to each vertically stacked and spaced apart first semiconductor channel material nanosheet of the first FET and to each vertically stacked and spaced apart second semiconductor channel material nanosheet of the second FET.

14 . A semiconductor device comprising:
a first field effect transistor (FET); a second FET stacked over the first FET; and a multi-dielectric material middle isolation structure located between the first FET and the second FET, wherein the multi-dielectric material middle isolation structure comprises a middle dielectric isolation structure having a middle dielectric isolation spacer surrounding the middle dielectric isolation structure.

15 . The semiconductor device of claim 14 , wherein the middle dielectric isolation structure is composed of a first dielectric material, and the middle dielectric isolation spacer is composed of a second dielectric material that is compositionally different from the first dielectric material.

16 . The semiconductor device of claim 14 , further comprising a protective layer located on a topmost surface and a bottommost surface of the middle dielectric isolation spacer.

17 . The semiconductor device of claim 14 , wherein a semiconductor channel region of the first FET is spaced apart from a bottommost surface of the middle dielectric isolation spacer, and a semiconductor channel region of the second FET is spaced apart from a topmost surface of the middle dielectric isolation spacer.

18 . The semiconductor device of claim 17 , wherein the semiconductor channel region of the first FET comprises a plurality of vertical stacked and spaced apart first semiconductor channel material nanosheets and the semiconductor channel region of the second FET comprises a plurality of vertical stacked and spaced apart second semiconductor channel material nanosheets.

19 . The semiconductor device of claim 14 , wherein the first FET and the second FET comprise a shared gate structure, and the shared gate structure directly contacts the middle dielectric isolation structure.

20 . The semiconductor device of claim 14 , further comprising a frontside back-end-of-the-line (BEOL) structure located above the second FET, and a backside interconnect structure located beneath the first FET, wherein the backside interconnect structure is electrically connected to a first source/drain region of the first FET, the frontside BEOL structure is electrically connected to a source/drain region of the second FET, and another first source/drain region of the first FET is electrically connected to the frontside BEOL structure.

Assignees

• IBM

Inventors

• Reboh Shay
• Sarkar Debarghya
• Sulehria Yasir
• Belyansky Michael P

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D62/115 Primary

  Dielectric isolations, e.g. air gaps · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title