Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025040132-A1
Application number	US-202418626728-A
Country	US
Kind code	A1
Filing date	Apr 4, 2024
Priority date	Jul 27, 2023
Publication date	Jan 30, 2025
Grant date	—

Abstract

A semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, where the substrate includes at least one first active pattern in the cell region and a second active pattern in the core region; a first trench defined by the at least one first active pattern; and a second trench defined by the second active pattern, where an inner sidewall of the first trench defines first recesses that extend into the at least one first active pattern, an inner sidewall of the second trench defines second recesses that extend into the second active pattern, a distance between two adjacent first recesses from among the first recesses in the vertical direction corresponds to a first height, a distance between two adjacent second recesses from among the second recesses in the vertical direction corresponds to a second height.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate that comprises a cell region, a core region, and a boundary region between the cell region and the core region, wherein the substrate comprises at least one first active pattern in the cell region and a second active pattern in the core region; a first trench defined by the at least one first active pattern; and a second trench defined by the second active pattern, wherein an inner sidewall of the first trench defines first recesses that extend into the at least one first active pattern, wherein the first recesses are spaced apart from each other in a vertical direction that intersects a top surface of the substrate, wherein an inner sidewall of the second trench defines second recesses that extend into the second active pattern, wherein the second recesses are spaced apart from each other in the vertical direction, wherein a distance between two adjacent first recesses from among the first recesses in the vertical direction corresponds to a first height, wherein a distance between two adjacent second recesses from among the second recesses in the vertical direction corresponds to a second height, and wherein the second height is greater than the first height.

2 . The semiconductor device of claim 1 , further comprising:
a third trench that is defined by the at least one first active pattern and comprising a width that is greater than a width of the first trench, wherein an inner sidewall of the third trench defines third recesses that extend into the at least one first active pattern, wherein the third recesses are spaced apart from each other in the vertical direction, a distance between two adjacent third recesses from among the third recesses in the vertical direction corresponds to a third height, and the third height is substantially equal to the first height.

3 . The semiconductor device of claim 1 , wherein:
the at least one first active pattern comprises a plurality of first active patterns, the plurality of first active patterns are spaced apart in a first horizontal direction and a second horizontal direction, wherein the first horizontal direction is parallel with the top surface of the substrate, and wherein the second horizontal direction is parallel with the top surface of the substrate and perpendicular to the first horizontal direction, each of the plurality of first active patterns comprises a long axis in a third horizontal direction that is parallel with the top surface of the substrate and intersects the first horizontal direction and the second horizontal direction, the first trench is between a first adjacent pair of first active patterns in the second horizontal direction from among the plurality of first active patterns, and a third trench is between a second adjacent pair of first active patterns in the third horizontal direction from among the plurality of first active patterns.

4 . The semiconductor device of claim 1 , further comprising:
a third trench that is in the boundary region and between the at least one first active pattern and the second active pattern, wherein an inner sidewall of the third trench defines third recesses that extend into the at least one first active pattern or the second active pattern, wherein the third recesses are spaced apart from each other in the vertical direction, a distance between two adjacent third recesses from among the third recesses in the vertical direction corresponds to a third height, and the third height is greater than the first height.

5 . The semiconductor device of claim 4 , wherein the third height is substantially equal to the second height.

6 . The semiconductor device of claim 4 , wherein a bottom of the second trench is a second distance from the substrate, wherein a bottom of the third trench is a third distance from the substrate, and wherein the second distance is less than or equal to the third distance.

7 . The semiconductor device of claim 4 , further comprising:
an isolation film in the third trench; and a capping pattern that overlaps at least a portion of a top surface of the isolation film, wherein the capping pattern extends from the cell region to the core region through the boundary region.

8 . The semiconductor device of claim 4 , wherein a width of the third trench is less than a width of the second trench.

9 . The semiconductor device of claim 1 , wherein at least a portion of the inner sidewall of the first trench between the two adjacent first recesses comprises a linear shape.

10 . The semiconductor device of claim 1 , wherein each of the first recesses and the second recesses comprises a nonlinear shape.

11 . The semiconductor device of claim 1 , wherein each of the inner sidewall of the first trench and the inner sidewall of the second trench comprises a nonlinear shape.

12 . A semiconductor device comprising:
a substrate comprising a cell region, a core region, and a boundary region between the cell region and the core region, wherein the substrate comprises first active patterns spaced apart in a first horizontal direction and a second horizontal direction in the cell region, wherein the first horizontal direction is parallel with a top surface of the substrate, and wherein the second horizontal direction is parallel with the top surface of the substrate and perpendicular to the first horizontal direction; a first trench and a second trench that are defined by the first active patterns; and an isolation film in the first trench and the second trench, wherein each of the first active patterns comprises a long axis in a third horizontal direction that is parallel with the top surface of the substrate and intersects the first horizontal direction and the second horizontal direction, the first trench is between a first adjacent pair of first active patterns in the second horizontal direction from among the first active patterns, the second trench is between a second adjacent pair of first active patterns in the third horizontal direction from among the first active patterns, a width of the second trench is greater than a width of the first trench, and a bottom of the first trench and a bottom of the second trench extend from the substrate by a substantially equal distance.

13 . The semiconductor device of claim 12 , wherein:
an inner sidewall of the first trench comprises first recesses that extend into a first one of the first active patterns, wherein the first one of the active patterns is adjacent to the first trench, and wherein the first recesses are spaced apart from each other in a vertical direction that intersects the top surface of the substrate, an inner sidewall of the second trench comprises second recesses that extend into a second one of the first active patterns, wherein the second one of the first active patterns is adjacent to the second trench, and wherein the second recesses are spaced from each other in the vertical direction, a distance between two adjacent first recesses from among the first recesses in the vertical direction corresponds to a first height, a distance between two adjacent second recesses from among the second recesses in the vertical direction corresponds to a second height, and the first height is substantially equal to the second height.

14 . The semiconductor device of claim 13 , further comprising:
a third trench that is defined by a second active pattern, wherein the second active pattern is in the boundary region, an inner sidewall of the third trench comprises third recesses that extend into the second active pattern, wherein the third reces

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Taeseop
• Kim Byunghoon
• Kim Junho
• Park Youngwook
• Park Jiho
• Lee Jungwoo
• Hwang Jihyun
• Choi Minho

Classifications

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/34 Primary

  the transistor being at least partially in a trench in the substrate · CPC title