Semiconductor process apparatus

Patent metadata

Field	Value
Publication number	US-2025028257-A1
Application number	US-202418436744-A
Country	US
Kind code	A1
Filing date	Feb 8, 2024
Priority date	Jul 17, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

A semiconductor process apparatus includes a light generator configured to output extreme ultraviolet (EUV) light having an EUV wavelength band, a mask stage configured to seat a mask reflecting the EUV light output from the light generator, a light-receiving optical unit including a plurality of mirrors generating output light by reflecting the EUV light reflected from the mask, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body, a power supply configured to apply a bias voltage to the reflective layer, and a substrate stage configured to seat a substrate to be irradiated with the output light.

First claim

What is claimed is:

1 . A semiconductor process apparatus comprising:
a light generator configured to output extreme ultraviolet (EUV) light having an EUV wavelength band; a mask stage configured to seat a mask, the mask being configured to reflect the EUV light output from the light generator; an optical light receiver including a plurality of mirrors that are configured to generate output light by reflecting the EUV light reflected from the mask, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body; a power supply configured to apply a bias voltage to the reflective layer; and a substrate stage configured to seat a substrate to be irradiated with the output light, wherein the reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer, and wherein the at least one graphene layer includes:
a base region including graphene, and
a plurality of pads attached to the base region and configured to enable the bias voltage to be applied to the plurality of pads.

2 . The semiconductor process apparatus of claim 1 , wherein the plurality of pads are arranged along an edge of the base region.

3 . The semiconductor process apparatus of claim 1 , wherein the power supply includes:
a first power supply circuit configured to output a first bias voltage, a first switch circuit connected between first pads of the plurality of pads and the first power supply circuit, and a second switch circuit connected between second pads of the plurality of pads and the first power supply circuit, the second pads being different from the first pads.

4 . The semiconductor process apparatus of claim 3 ,
wherein the first switch circuit includes a first multiplexer, and wherein the second switch circuit includes a second multiplexer.

5 . The semiconductor process apparatus of claim 3 ,
wherein the first switch circuit is configured to determine a first selection pad among the first pads, wherein the second switch circuit is configured to determine a second selection pad among the second pads, and wherein the first power supply circuit is configured to apply the first bias voltage to the first selection pad and the second selection pad.

6 . The semiconductor process apparatus of claim 5 , wherein the first switch circuit and the second switch circuit are configured to determine the first selection pad and the second selection pad based on a location and an area of an irradiation area in which the EUV light is irradiated in at least one mirror of the plurality of mirrors.

7 . The semiconductor process apparatus of claim 3 , wherein the power supply further includes:
a second power supply circuit configured to output a second bias voltage, a third switch circuit connected between third pads of the plurality of pads and the second power supply circuit, and a fourth switch circuit connected between fourth pads of the plurality of pads and the second power supply circuit, the fourth pads being different from the third pads.

8 . The semiconductor process apparatus of claim 7 ,
wherein the first switch circuit is configured to determine a first selection pad among the first pads, wherein the second switch circuit is configured to determine a second selection pad among the second pads, wherein the third switch circuit is configured to determine a third selection pad among the third pads, and wherein the second switch circuit is configured to determine a fourth selection pad among the fourth pads, wherein the first power supply circuit is configured to apply a first bias voltage to the first selection pad and the second selection pad for a first time period, and wherein the second power supply circuit is configured to apply a second bias voltage to the third selection pad and the fourth selection pad for a second time period after the first time period.

9 . A semiconductor process apparatus comprising:
a mask stage configured to seat a mask; a substrate stage configured to seat a substrate; a light generator configured to output extreme ultraviolet light (EUV) having an extreme ultraviolet EUV wavelength band to the mask; and an optical light receiver including a plurality of mirrors configured to reflect the EUV light reflected from the mask and enable the EUV light to be incident to the substrate, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body, wherein the reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer.

10 . The semiconductor process apparatus of claim 9 , wherein a thickness of the graphene layer is less than a thickness of each of the plurality of silicon layers and the plurality of molybdenum layers.

11 . The semiconductor process apparatus of claim 9 , wherein the reflective layer further includes a plurality of metal layers disposed between the plurality of silicon layers and the plurality of molybdenum layers.

12 . The semiconductor process apparatus of claim 11 , wherein the plurality of metal layers include:
at least one first metal layer including yttrium or niobium, and at least one second metal layer including ruthenium.

13 . The semiconductor process apparatus of claim 11 ,
wherein the graphene layer includes a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers and the plurality of molybdenum layers, and wherein the second surface is in contact with at least one of the plurality of metal layers.

14 . The semiconductor process apparatus of claim 9 ,
wherein the graphene layer includes a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers, and wherein the second surface is in contact with one of the plurality of molybdenum layers.

15 . The semiconductor process apparatus of claim 9 ,
wherein the graphene layer includes a first surface and a second surface parallel to the first surface, wherein the first surface is a surface exposed externally, and wherein the second surface contacts one of the plurality of silicon layers and the plurality of molybdenum layers.

16 . The semiconductor process apparatus of claim 9 ,
wherein the graphene layer includes a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers and the plurality of molybdenum layers, and wherein the second surface is in contact with one surface of the mirror body.

17 . The semiconductor process apparatus of claim 9 ,
wherein the graphene layer includes a first graphene layer and a second graphene layer, wherein each of the first graphene layer and the second graphene layer includes a first surface and a second surface parallel to the first surface, wherein, in each of the first graphene layer and the second graphene layer, the first surface is located farther from the mirror body than the second surface, wherein the first surface of the first graphene layer is in contact with a first silicon layer of the plurality of silicon layers, and wherein the second surface of the first graphene layer is in contact with a first molybdenum layer of the plur

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Kyoungwhan
• Lee Dahae
• Jeang Eunhee
• Cho Chulmin
• Kang Kyungwon

Classifications

• H10P72/53

  using optical controlling means · CPC title

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• G02B7/008

  with means for compensating for changes in temperature or for controlling the temperature; thermal stabilisation · CPC title

• G02B5/0875

  the reflecting layers comprising two or more metallic layers · CPC title

• G03F7/70891

  Temperature · CPC title