Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-2025015004-A1
Application number	US-202418894586-A
Country	US
Kind code	A1
Filing date	Sep 24, 2024
Priority date	May 28, 2013
Publication date	Jan 9, 2025
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . An IC assembly, comprising:
a package substrate having a bridge therein, wherein the bridge comprises a silicon substrate, the package substrate comprising:
a dielectric layer over the bridge;
a first interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the first interconnect piece is disposed extending in and over the dielectric layer, wherein the first interconnect piece comprises copper;
a first layer on the first interconnect piece, wherein the first layer comprises nickel;
a second interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the second interconnect piece is disposed extending in and over the dielectric layer, wherein the second interconnect piece comprises copper;
a second layer on the second interconnect piece, wherein the second layer comprises nickel;
a first interconnect structure, wherein the first interconnect structure is laterally spaced from a first side of the bridge, wherein the first interconnect structure extends through the dielectric layer;
a second interconnect structure, wherein the second interconnect structure is laterally spaced from a second side of the bridge, wherein the second interconnect structure extends through the dielectric layer;
a first die electrically coupled with the first interconnect piece and the first interconnect structure of the package substrate; and a second die electrically coupled with the second interconnect piece and the second interconnect structure of the package substrate.

2 . The IC assembly of claim 1 , wherein the first die is a processor and the second die is a memory.

3 . The IC assembly of claim 1 , wherein the first die is an application specific integrated circuit and the second die is a memory.

4 . The IC assembly of claim 1 , wherein the dielectric layer is in contact with the bridge.

5 . The IC assembly of claim 1 , wherein the first die is disposed over the bridge having a partial lateral overlap, wherein the second die is disposed over the bridge having a partial lateral overlap.

6 . The IC assembly of claim 1 , wherein the bridge is embedded in the package substrate.

7 . The IC assembly of claim 1 , wherein the first layer and the second layer are manufacturable at the same time.

8 . An IC assembly, comprising:
a package substrate having bridge thereon, wherein the bridge comprises a silicon substrate, the package substrate comprising:
a dielectric layer over the bridge;
a first interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the first interconnect piece is disposed extending in and over the dielectric layer, wherein the first interconnect piece comprises copper;
a first layer on the first interconnect piece, wherein the first layer comprises nickel;
a second interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the second interconnect piece is disposed extending in and over the dielectric layer, wherein the second interconnect piece comprises copper;
a second layer on the second interconnect piece, wherein the second layer comprises nickel;
a first interconnect structure, wherein the first interconnect structure is laterally spaced from a first side of the bridge, wherein the first interconnect structure extends through the dielectric layer;
a second interconnect structure, wherein the second interconnect structure is laterally spaced from a second side of the bridge, wherein the second interconnect structure extends through the dielectric layer;
a first die electrically coupled with the first interconnect piece and the first interconnect structure of the package substrate; and a second die electrically coupled with the second interconnect piece and the second interconnect structure of the package substrate.

9 . The IC assembly of claim 8 , wherein the first die is a processor and the second die is a memory.

10 . The IC assembly of claim 8 , wherein the first die is an application specific integrated circuit and the second die is a memory.

11 . The IC assembly of claim 8 , wherein the dielectric layer is in contact with the bridge.

12 . The IC assembly of claim 8 , wherein the first die is disposed over the bridge having a partial lateral overlap, wherein the second die is disposed over the bridge having a partial lateral overlap.

13 . The IC assembly of claim 8 , wherein the first layer and the second layer are manufacturable at the same time.

14 . A computing device, comprising:
a board; and an IC assembly coupled to the board, the IC assembly comprising:
a package substrate having a bridge therein or thereon, wherein the bridge comprises a silicon substrate, the package substrate comprising:
a dielectric layer over the bridge;
a first interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the first interconnect piece is disposed extending in and over the dielectric layer, wherein the first interconnect piece comprises copper;
a first layer on the first interconnect piece, wherein the first layer comprises nickel;
a second interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the second interconnect piece is disposed extending in and over the dielectric layer, wherein the second interconnect piece comprises copper;
a second layer on the second interconnect piece, wherein the second layer comprises nickel;
a first interconnect structure, wherein the first interconnect structure is laterally spaced from a first side of the bridge, wherein the first interconnect structure extends through the dielectric layer;
a second interconnect structure, wherein the second interconnect structure is laterally spaced from a second side of the bridge, wherein the second interconnect structure extends through the dielectric layer;

a first die electrically coupled with the first interconnect piece and the first interconnect structure of the package substrate; and a second die electrically coupled with the second interconnect piece and the second interconnect structure of the package substrate.

15 . The IC assembly of claim 14 , wherein the package substrate has the bridge therein.

16 . The IC assembly of claim 14 , wherein the package substrate has the bridge thereon.

17 . The IC assembly of claim 14 , further comprising:
a memory coupled to the board.

18 . The IC assembly of claim 14 , further comprising:
a communication chip coupled to the board.

19 . The IC assembly of claim 14 , further comprising:
a graphics CPU coupled to the board.

20 . The IC assembly of claim 14 , further comprising:
a GPS coupled to the board.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title