Memory device

Patent metadata

Field	Value
Publication number	US-2024421081-A1
Application number	US-202418631666-A
Country	US
Kind code	A1
Filing date	Apr 10, 2024
Priority date	Jun 19, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, and a memory cell extending in a vertical direction between the first conductive line and the second conductive line. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer, which are sequentially stacked on the first conductive line. The switching pattern includes a chalcogenide layer including a chalcogen element of group VI of the periodic table, and an element of group IV and an element of group V of the periodic table, which are chemically bonded to the group VI chalcogen element. The switching pattern is configured to have a three-level concentration gradient of the group IV element or the group V element in the vertical direction.

First claim

What is claimed is:

1 . A memory device comprising:
a first conductive line extending in a first horizontal direction; a second conductive line extending in a second horizontal direction; and a memory cell extending in a vertical direction between the first conductive line and the second conductive line, wherein the memory cell comprises a lower electrode layer, a switching pattern, and an upper electrode layer, wherein the lower electrode layer, the switching pattern, and the upper electrode layer are sequentially stacked on the first conductive line, wherein the switching pattern comprises a chalcogenide layer including:
a group VI chalcogen element of a periodic table, and
a combination of a group IV element and a group V element of the periodic table,
wherein the combination is chemically bonded to the group VI chalcogen element, and
wherein the switching pattern has a three-level concentration gradient of the group IV element or the group V element in the vertical direction.

2 . The memory device of claim 1 , wherein the switching pattern comprises a first interface region formed on the lower electrode layer, a core region formed on the first interface region, and a second interface region formed on the core region.

3 . The memory device of claim 2 , wherein a concentration of the group V element in each of the first interface region and the second interface region is higher than a concentration of the group V element in the core region.

4 . The memory device of claim 2 , wherein a concentration of the group IV element in each of the first interface region and the second interface region is lower than a concentration of the group IV element in the core region.

5 . The memory device of claim 2 , wherein a concentration of the group VI chalcogen element in each of the first interface region and the second interface region is the same as a concentration of the group VI chalcogen element in the core region.

6 . The memory device of claim 1 , wherein the group VI chalcogen element comprises at least one of tellurium (Te), selenium (Se), or sulfur (S),
wherein the group V element comprises at least one of arsenic (As), antimony (Sb), or phosphorous (P), and wherein the group IV element comprises at least one of silicon (Si) or germanium (Ge).

7 . The memory device of claim 1 , wherein the switching pattern further comprises a group III doping element of the periodic table.

8 . The memory device of claim 7 , wherein the group III doping element comprises at least one of indium (In), gallium (Ga), or aluminum (Al).

9 . The memory device of claim 1 , wherein the switching pattern is configured so that a concentration gradient of a bonded element including the combination and the group VI chalcogen element remains unchanged before and after applying an operating voltage to the switching pattern.

10 . A memory device comprising:
a first conductive line extending in a first horizontal direction; a second conductive line extending in a second horizontal direction; and a memory cell extending in a vertical direction between the first conductive line and the second conductive line, wherein the memory cell comprises a lower electrode layer, a switching pattern, and an upper electrode layer, wherein the lower electrode layer, the switching pattern, and the upper electrode layer are sequentially stacked on the first conductive line, wherein the switching pattern comprises a chalcogenide layer including: a group VI chalcogen element of a periodic table, and a combination of a group IV element and a group V element of the periodic table, wherein the combination is chemically bonded to the group VI chalcogen element, wherein the switching pattern comprises a first interface region on the lower electrode layer, a core region on the first interface region, and a second interface region on the core region, wherein a concentration of the group IV element in each of the first interface region and the second interface region is lower than a concentration of the group IV element in the core region, and wherein a concentration of the group V element in each of the first interface region and the second interface region is higher than a concentration of the group V element in the core region.

11 . The memory device of claim 10 , wherein the group VI chalcogen element comprises at least one of tellurium (Te), selenium (Se), or sulfur (S), the group V element comprises at least one of arsenic (As), antimony (Sb), or phosphorous (P), and the group IV element comprises at least one of silicon (Si) or germanium (Ge).

12 . The memory device of claim 11 , wherein the first interface region and the second interface region comprise about 10 atom % to about 20 atom % of a group IV element, about 25 atom % to about 40 atom % of a group V element, and about 40 atom % to about 65 atom % of a group VI chalcogen element.

13 . The memory device of claim 11 , wherein the core region comprises about 15 atom % to about 25 atom % of a group IV element, about 20 atom % to about 30 atom % of a group V element, and about 45 atom % to about 65 atom % of a group VI chalcogen element.

14 . The memory device of claim 11 , wherein the switching pattern further comprises a group III doping element of the periodic table.

15 . The memory device of claim 14 , wherein the group III doping element comprises at least one of indium (In), gallium (Ga), or aluminum (Al).

16 . The memory device of claim 10 , wherein the switching pattern is configured so that a concentration gradient of a bonded element including the combination and the group VI chalcogen element remains unchanged when a polarity of an operating voltage applied to the lower electrode layer and the upper electrode layer changes.

17 . A memory device comprising:
a first conductive line extending in a first horizontal direction; a second conductive line extending in a second horizontal direction; and a memory cell extending in a vertical direction between the first conductive line and the second conductive line, wherein the memory cell comprises a lower electrode layer, a switching pattern, and an upper electrode layer, wherein the lower electrode layer, the switching pattern, and the upper electrode layer are sequentially stacked on the first conductive line, wherein the switching pattern comprises a chalcogenide layer including: a group VI chalcogen element of a periodic table; and a combination of a group IV element and a group V element of the periodic table, wherein the combination is, chemically bonded to the group VI chalcogen element, wherein the switching pattern comprises a first interface region formed on the lower electrode layer, a core region formed on the first interface region, and a second interface region formed on the core region, wherein the core region comprises an impurity layer of a first conductive type, and wherein the first interface region and the second interface region comprise an impurity layer of a second conductive type that is opposite to the first conductive type.

18 . The memory device of claim 17 , wherein the core region comprises a P-type impurity layer, and the first interface region and the second interface region comprise an N-type impurity layer.

19 . The memory device of claim 17 , wherein a concentration of the group IV element in each of the first interface region and the second interface region is lower than a concentration of the group IV element in the core region, and a concentration of the group V element in each of the f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Seulji

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title