Semiconductor package

Patent metadata

Field	Value
Publication number	US-2024421034-A1
Application number	US-202418403936-A
Country	US
Kind code	A1
Filing date	Jan 4, 2024
Priority date	Jun 14, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate disposed on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.

2 . The semiconductor package of claim 1 , wherein the base layer comprises glass.

3 . The semiconductor package of claim 1 , wherein the base layer comprises ceramic.

4 . The semiconductor package of claim 1 , wherein the second insulating layer extends along the upper surface of the base layer and the upper surface of the molding layer.

5 . The semiconductor package of claim 4 ,
wherein the base layer comprises glass, the molding layer comprises an epoxy molding compound, and the second insulating layer comprises polyimide.

6 . The semiconductor package of claim 1 , wherein the second conductive patterns comprise a conductive via pattern extending in the second insulating layer and contacting an upper surface of the through electrode.

7 . The semiconductor package of claim 6 , wherein a horizontal width of the conductive via pattern decreases as it approaches the upper surface of the through electrode.

8 . The semiconductor package of claim 7 , wherein the upper surface of the through electrode comprises a first portion and a second portion, wherein the first portion is in contact with the conductive via pattern, and the second portion is in contact with the second insulating layer.

9 . The semiconductor package of claim 1 , wherein the connection substrate is connected to the first redistribution structure through a first connection bump.

10 . The semiconductor package of claim 1 , further comprising a bridge chip disposed in the molding layer and including a bridge circuit pattern configured to electrically connect between each of the plurality of semiconductor devices.

11 . The semiconductor package of claim 10 , further comprising
a conductive pillar disposed on the bridge chip, and configured to electrically connect the bridge circuit pattern to the second conductive patterns, wherein the molding layer extends along sidewalls of the conductive pillar.

12 . The semiconductor package of claim 10 , wherein the base layer of the connection substrate comprises a plurality of segments spaced apart from each other with the bridge chip therebetween.

13 . The semiconductor package of claim 10 , wherein the base layer of the connection substrate has a annular shape surrounding the bridge chip.

14 . A semiconductor package comprising:
a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate disposed on the first redistribution structure, and including a base layer and a through electrode configured to penetrate the base layer, wherein the base layer comprises glass; a molding layer at least partially surrounding the connection substrate on the first redistribution structure and including an epoxy mold compound; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer, and wherein the second insulating layer extends along the upper surface of the base layer and the upper surface of the molding layer.

15 . The semiconductor package of claim 14 ,
wherein the second conductive patterns comprise a conductive via pattern extending in the second insulating layer and contacting an upper surface of the through electrode, and wherein a horizontal width of the conductive via pattern decreases as it approaches the upper surface of the through electrode.

16 . The semiconductor package of claim 15 ,
wherein the upper surface of the through electrode comprises a first portion and a second portion, wherein the first portion is in contact with the conductive via pattern, and the second portion is in contact with the second insulating layer, and wherein the second conductive patterns further comprise a seed metal pattern provided between the conductive via pattern and the upper surface of the through electrode.

17 . A semiconductor package comprising:
a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate mounted on the first redistribution structure, and including a base layer and a through electrode configured to penetrate the base layer, wherein the base layer includes a first material; first connection bumps disposed between the connection substrate and the first redistribution structure; a bridge chip mounted on the first redistribution structure and spaced apart from the connection substrate in a lateral direction, wherein the bridge chip includes a bridge circuit pattern; second connection bumps disposed between the bridge chip and the first redistribution structure; a plurality of conductive pillars disposed on the bridge chip, and electrically connected to the bridge circuit pattern; a molding layer at least partially surrounding the connection substrate and the bridge chip on the first redistribution structure and including a second material; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns; and a plurality of semiconductor devices spaced apart from each other and disposed on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer, wherein the second insulating layer extends along the upper surface of the base layer and the upper surface of the molding layer, and wherein the second conductive patterns comprise a conductive via pattern extending in the second insulating layer and contacting an upper surface of the through electrode.

18 . The semiconductor package of claim 17 , wherein the molding layer at least partially surrounds each of the first connection bumps, each of the second connection bumps, and each of the conductive pillars.

19 . The semiconductor package of claim 17 ,
wherein the base layer comprises glass, the molding layer comprises an epoxy molding compound, and the second insulating layer comprises polyimide.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Byungho
• Ko Youngchan
• Kim Gyeongho
• Lee Yongkoon
• Cho Myungdo

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title