Fan out package-on-package with adhesive die attach

Patent metadata

Field	Value
Publication number	US-2019355659-A1
Application number	US-201815981830-A
Country	US
Kind code	A1
Filing date	May 16, 2018
Priority date	May 16, 2018
Publication date	Nov 21, 2019
Grant date	—

Abstract

Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.

First claim

What is claimed is:

1 . A microelectronic device package assembly, comprising:
a first chip comprising a first integrated circuit (IC); a via structure adjacent to the first chip; a first package material between a sidewall of the first chip and a sidewall of the via structure; one or more redistribution layers electrically coupled to a first side of the first chip and to a first side of the via structure; a second chip comprising a second IC, wherein the second chip is over a second side of the first chip, opposite the first side, and wherein the second chip is electrically coupled to a second side of the via structure; and a second package material between at least a portion of the first chip and at least a portion of the second chip.

2 . The device package assembly of claim 1 , wherein the first package material is between the second package material and the second side of the first chip.

3 . The device package assembly of claim 2 , wherein:
the second package material is between at least a portion of the via structure and at least a portion of the second chip; and the first package material is between the second package material and the second side of the via structure.

4 . The device package assembly of claim 1 , further comprising a plurality of interconnects electrically coupling the second chip to the via structure.

5 . The device package assembly of claim 3 , wherein the interconnects comprise solder features and the second package material is absent from between the solder features.

6 . The device package assembly of claim 5 , further comprising a third package material between the solder features.

7 . The device package assembly of claim 6 , wherein the third package material is between the second chip and the first package material, and wherein a sidewall of the third package material is adjacent to a sidewall of the second package material.

8 . The device package assembly of claim 4 , wherein:
the interconnects are aligned in a row adjacent to a first edge of the second chip; a first portion of a footprint of the second chip occupied by the row of interconnects overhangs beyond an edge of the second package material; and a second portion of the footprint of the second chip not occupied by the row of interconnects is in contact with the second package material.

9 . The device package assembly of claim 8 , wherein the second package material extends beyond at least a second edge of the second chip, opposite the first edge of the second chip.

10 . The device package assembly of claim 1 , wherein:
the first package material comprises a first epoxy; the second package material comprises a second epoxy; and wherein the assembly further comprises a third epoxy over the second chip.

11 . A packaged microelectronic device, comprising:
a microprocessor chip, wherein a first side of the microprocessor chip is electrically coupled to one or more redistribution layers of a package; a via structure adjacent to the microprocessor chip, wherein a first side of the via structure is electrically coupled to the one or more redistribution layers; a first package material between a sidewall of the microprocessor chip and a sidewall of the via structure; a memory chip over a second side of the microprocessor chip, over a second side of the via structure, and electrically coupled to the second side of the via structure; and a second package material between the microprocessor chip and the memory chip.

13 . The microelectronic device of claim 12 , wherein the microprocessor comprises a baseband radio processor, and wherein the memory chip comprises a DRAM.

14 . The microelectronic device of claim 12 , wherein:
the first package material is over the second side of the processor chip and the memory chip; the second package material is over the first package material; the memory chip is electrically coupled to the second side of the via structure through a plurality of interconnects that each extend through a thickness of the first package material that is over the second side of the memory chip; and an edge of the second package material proximal to the conductive features is laterally spaced apart from a sidewall of at least one of the interconnects.

15 . The microelectronic device of claim 14 , further comprising a third package material between the interconnects and between the edge of the second package material and the sidewall of at least one of the interconnects.

16 . A method of fabricating a microelectronic package assembly, the method comprising:
receiving a workpiece, the workpiece comprising a first chip and a via structure embedded within a first package material, wherein a first side of the first chip and a first side of the via structure are electrically coupled to one or more redistribution layers of a package; applying a second package material above a second side of at least a portion of the first chip; adhering one or more components to the second package material, the components including a second chip and a plurality of interconnects electrically coupled to the second chip; and reflowing the plurality of interconnects to electrically couple the second chip to a second side of the via structure.

17 . The method of claim 16 , wherein applying the second package material comprises at least one of screen printing an adhesive material, patterning a layer of an adhesive material, needle dispensing an adhesive material, or pick-and-placing a pre-fabricated pad of an adhesive material.

18 . The method of claim 16 , further comprising assembling the workpiece prior to applying the second package material, the assembling comprising:
molding the first chip and the via structure within the first package material; forming the one or more redistribution layers coupled to the first side of the first chip and to the first side of the via structure; and forming a plurality of second interconnects on a first side of the first package material and coupled to the one or more redistribution layers.

19 . The method of claim 18 , further comprising forming a through-mold via through a thickness of the first package material that is over the second side of the via structure.

20 . The method of claim 16 , further comprising pre-curing the second package material prior to attaching the one or more components.

21 . The method of claim 16 , further comprising underfilling a third package material between the plurality of interconnects electrically coupled to the second chip.

22 . The method of claim 16 , further comprising:
coating, molding, or spraying a final package material over the second chip.

Assignees

• Intel Ip Corp

Inventors

• O'Sullivan David
• Waidhas Bernd
• Huber Thomas

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title