Extended floating-point range processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-2024419444-A1
Application number	US-202318210635-A
Country	US
Kind code	A1
Filing date	Jun 15, 2023
Priority date	Jun 15, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A processor of an aspect includes decoder circuitry to decode an instruction indicating a source floating-point operand, having a floating-point data element, and indicating a destination register. The element has a sign bit, an N-bit first exponent value, and M bits. Execution circuitry of the processor is to interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones, and interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones. The execution unit is to perform an operation on the source floating-point operand to generate a result floating-point operand, and to store the result floating-point operand in the destination register.

First claim

What is claimed is:

1 . An apparatus comprising:
decoder circuitry to decode an instruction, the instruction to indicate at least a source floating-point operand and a destination register, the source floating-point operand to have at least a floating-point data element, the floating-point data element to have a sign bit, an N-bit first exponent value, and M bits; and execution circuitry coupled with the decoder circuitry, the execution circuitry to perform operations corresponding to the instruction, including to:
interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones;
interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones;
perform an operation specified by the instruction on said at least the source floating-point operand to generate a result floating-point operand; and
store the result floating-point operand in the destination register.

2 . The apparatus of claim 1 , wherein the second exponent value comprises a plurality of least significant bits of the M bits, and wherein the less than M-bit significand comprises a plurality of bits more significant than the plurality of least significant bits.

3 . The apparatus of claim 2 , wherein the second exponent value, and the less than M-bit significand, together include M bits.

4 . The apparatus of claim 1 , wherein, when the N-bit first exponent value is all zeroes, the execution circuitry is to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

5 . The apparatus of claim 4 , wherein the second exponent value has enough bits to be able to encode any one of at least M different values.

6 . The apparatus of claim 4 , wherein, when the second exponent value has a given value, the execution circuitry is to set a sticky bit equal to an implicit most significant significand bit for the floating-point data element.

7 . The apparatus of claim 4 , wherein one of:
the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes from two to six of the M bits, and the less than M-bit significand includes from forty-six to fifty of the M bits; the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes from two to five of the M bits, and the less than M-bit significand includes from eighteen to twenty-one of the M bits; the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to four of the M bits, and the less than M-bit significand includes from six to eight of the M bits; and the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes from two to four of the M bits, and the less than M-bit significand includes from three to five of the M bits.

8 . The apparatus of claim 1 , wherein, when the N-bit first exponent value is all ones, the execution circuitry is to combine the second exponent value with the N-bit first exponent value.

9 . The apparatus of claim 8 , wherein one of:
the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes from three to eleven of the M bits, and the less than M-bit significant includes from forty-one to forty-nine of the M bits; the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes from three to eight of the M bits, and the less than M-bit significant includes from fifteen to twenty of the M bits; the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to five of the M bits, and the less than M-bit significant includes from five to eight of the M bits; and the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes from two to six of the M bits, and the less than M-bit significant includes from one to five of the M bits.

10 . The apparatus of claim 1 , wherein, when the N-bit first exponent value is all ones, the execution circuitry is not to interpret the floating-point data as a Not a Number (NaN) or as infinity.

11 . The apparatus of claim 1 , wherein the apparatus is to use a value to determine a number of bits of the second exponent value, and wherein the apparatus is either to read the value from a register or obtain the value from either a prefix or an immediate of the instruction.

12 . A method comprising:
decoding an instruction, the instruction indicating at least a source floating-point operand and a destination register, the source floating-point operand having at least a floating-point data element, the floating-point data element having a sign bit, an N-bit first exponent value, and M bits; and performing operations corresponding to the instruction, including:
interpreting the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones;
interpreting the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones;
performing an operation specified by the instruction on said at least the source floating-point operand to generate a result floating-point operand; and
storing the result floating-point operand in the destination register.

13 . The method of claim 12 , wherein the second exponent value comprises a plurality of least significant bits of the M bits, and wherein the less than M-bit significand comprises a plurality of bits more significant than the plurality of least significant bits.

14 . The method of claim 12 , wherein, when the N-bit first exponent value is all zeroes, the execution circuitry is to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.

15 . The method of claim 14 , wherein, when the second exponent value has a given value, the execution circuitry is to set a sticky bit equal to an implicit most significant significand bit for the floating-point data element.

16 . The method of claim 12 , wherein, when the N-bit first exponent value is all ones, the execution circuitry is to combine the second exponent value with the N-bit first exponent value.

17 . A system to process instructions comprising:
a processor including:
decoder circuitry to decode an instruction, the instruction to indicate at least a source floating-point operand and a destination register, the source floating-point operand to have at least a floating-poin

Assignees

• Intel Corp

Inventors

• Langhammer Martin
• Heinecke Alexander F

Classifications

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3013 Primary

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30014

  with variable precision · CPC title