Programmable integrated circuit underlay

Patent metadata

Field	Value
Publication number	US-2024394448-A1
Application number	US-202418796279-A
Country	US
Kind code	A1
Filing date	Aug 6, 2024
Priority date	Jun 1, 2020
Publication date	Nov 28, 2024
Grant date	—

Abstract

A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.

First claim

What is claimed is:

1 . A method of using design tools to implement a logic circuit on a programmable device, comprising:
extracting an underlay from a routing network on the programmable device, wherein the extracted underlay comprises a subset of routing wires in the routing network satisfying target routing constraints; and mapping the logic circuit to the extracted underlay prioritizing mapping to the extracted underlay by prioritizing portions of the logic circuit corresponding to a first operation type and de-prioritizing a second portion of the logic circuit corresponding to a second operation type.

2 . The method of claim 1 , wherein extracting the underlay comprises accessing a database to obtain information on the routing network.

3 . The method of claim 2 , wherein extracting the underlay further comprises receiving the target routing constraints.

4 . The method of claim 3 , wherein the target routing constraints comprise source coordinate constraints, timing requirement constraints, speed requirement constraints, types of routing resource constraints, routing direction constraints, or crosstalk property constraints.

5 . The method of claim 1 , further comprising using the extracted underlay on at least one other region on the programmable device.

6 . The method of claim 1 , wherein the extracted underlay comprises a plurality of adjacent programmable logic blocks.

7 . The method of claim 1 , wherein the extracted underlay comprises a plurality of 2:1 datapath reduction operators.

8 . The method of claim 7 , wherein the plurality of 2:1 datapath reduction operators comprises a plurality of 2:1 multiplexers.

9 . The method of claim 7 , wherein the plurality of 2:1 datapath reduction operators comprises a plurality of adders.

10 . The method of claim 7 , wherein the plurality of 2:1 datapath reduction operators comprises a plurality of logic gates.

11 . The method of claim 7 , wherein the plurality of 2:1 datapath reduction operators have different ingress and egress patterns.

12 . An integrated circuit, comprising:
a programmable routing network; and a logic circuit comprising:
a first portion implementing a first operation type using an underlay extracted from the programmable routing network; and
a second portion implementing a second operation type, wherein the extracted underlay comprises a wiring pattern within the programmable routing network satisfying target routing constraints that comprise prioritizing implementing the first portion on the underlay over implementing the second portion on the underlay.

13 . The integrated circuit of claim 12 , wherein the extracted underlay comprises a plurality of programmable logic blocks.

14 . The integrated circuit of claim 12 , wherein the extracted underlay comprises a plurality of adjacent programmable logic blocks.

15 . The integrated circuit of claim 14 , wherein at least one of the plurality of programmable logic blocks in the extracted underlay is used to implement a 2:1 datapath reduction operator.

16 . The integrated circuit of claim 15 , wherein the 2:1 datapath reduction operator comprises a 2:1 multiplexer.

17 . The integrated circuit of claim 15 , wherein the 2:1 datapath reduction operator comprises an adder.

18 . The integrated circuit of claim 15 , wherein the 2:1 datapath reduction operator comprises a logic gate.

19 . The integrated circuit of claim 12 , wherein the target routing constraints comprise a timing constraint.

20 . A non-transitory, computer-readable storage medium having stored thereon instructions, that when executed by a processor, are configured to cause the processor to:
extract an underlay from a routing network on a programmable device, wherein the extracted underlay comprises a subset of routing wires in the routing network satisfying target routing constraints; and map a first portion of a logic circuit to the extracted underlay and a second portion of the logic circuit to the routing network at least partially outside of the underlay, wherein the first portion corresponds to a first operation type and the second portion corresponds to a second operation type and the target routing constraints comprises prioritizing mapping of the first operation type to the underlay over prioritizing the routing of the second operation type to the underlay.

Assignees

• Intel Corp

Inventors

• Baeckler Gregg William
• Langhammer Martin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/337

  Design optimisation · CPC title