Semiconductor device structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-2024387626-A1
Application number	US-202418786260-A
Country	US
Kind code	A1
Filing date	Jul 26, 2024
Priority date	May 11, 2021
Publication date	Nov 21, 2024
Grant date	—

Abstract

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

First claim

What is claimed is:

1 . A method for forming a semiconductor device structure, comprising:
forming nanostructures over a substrate; forming a gate structure surrounding and over the nanostructures; forming spacer layers over opposite sides of the gate structure over the nanostructures; forming a dummy layer over sidewalls of the spacer layers; forming contact structures beside the gate structure; removing the dummy layer to form an air spacer between the spacer layers and the contact structures; and depositing a sealing liner layer over the gate structure, the contact structure, and the air spacer.

2 . The method of claim 1 , further comprising:
before the forming of the contact structures, forming a protection layer over sidewalls of the dummy layer, wherein the air spacer is formed between the spacer layers and the protection layer.

3 . The method of claim 1 , further comprising:
annealing the dummy layer to form a silicide layer in a portion of the dummy layer in contact with the contact structures, wherein the air spacer is formed between the spacer layers and the silicide layer.

4 . The method of claim 1 , further comprising:
forming a filling film over the seal liner layer; and depositing a contact etch stop layer over the filling film.

5 . The method of claim 4 , further comprising:
forming a void in the filling film over the gate structure while forming the filling film.

6 . The method of claim 1 , further comprising:
forming source/drain epitaxial structures beside the nanostructures, wherein the forming of the dummy layer comprises forming the dummy layer on the source/drain epitaxial structures, wherein the removing of the dummy layer comprises etching a portion of the source/drain epitaxial structures below the dummy layer.

7 . The method of claim 6 , wherein the dummy layer includes a semiconductor material.

8 . The method of claim 1 , wherein
before the forming of the dummy layer, forming a hard mask layer over the gate structure; and removing the hard mask layer when removing the dummy layer.

9 . The method of claim 8 , wherein the dummy layer and the hard mask layer are made of a same material.

10 . The method of claim 1 , further comprising:
recessing the gate structure after the forming of the spacer layers; and forming a hard mask layer over the recessed gate structure.

11 . The method of claim 10 , wherein the recessing of the gate structure also recesses the spacer layers, and the hard mask layer is formed over top surfaces of the spacer layers.

12 . The method of claim 11 , wherein after the recessing of the gate structure, a top surface of the spacer layers is substantially level with a top surface of the hard mask layer.

13 . A method for forming a semiconductor device structure, comprising:
forming one or more semiconductor channels over a substrate; forming a gate structure surrounding and over the one or more semiconductor channels; forming spacer layers over opposite sides of the gate structure; recessing the gate structure and the spacer layers to form a gate trench; forming a hard mask in the gate trench and over the gate structure and gate spacers; forming a dummy layer over sidewalls of the hard mask and spacer layers; forming contact structures beside the dummy layer; and removing the dummy layer to form an air spacer between the spacer layers and the contact structures.

14 . The method of claim 13 , further comprising:
depositing a sealing liner layer over the gate structure, the contact structures, and the air spacer.

15 . The method of claim 14 , wherein after the depositing of the sealing liner layer, a top surface of the air spacer is substantially level with a top surface of the contact structures.

16 . The method of claim 13 , further comprising:
depositing a gate fill metal over the recessed gate structure, wherein the hard mask is formed over the gate fill metal.

17 . The method of claim 13 , wherein the removing of the dummy layer simultaneously removes the hard mask.

18 . A method for forming a semiconductor device structure, comprising:
forming one or more semiconductor channels over a substrate; forming source/drain epitaxial features adjacent the one or more semiconductor channels; forming a gate structure surrounding and over the one or more semiconductor channels; forming spacer layers over opposite sides of the gate structure; forming a hard mask over the gate structure and gate spacers; forming a dummy layer over sidewalls of the hard mask and spacer layers; forming contact structures over the source/drain epitaxial features and beside the dummy layer; removing the dummy layer and the hard mask, wherein the removing of the dummy layer forms an air spacer between the spacer layers and the contact structures; and depositing a sealing liner layer over the gate structure, the contact structure, and the air spacer.

19 . The method of claim 18 , further comprising:
before the forming of the contact structures, forming a protection layer over sidewalls of the dummy layer, wherein the air spacer is formed between the spacer layers and the protection layer.

20 . The method of claim 18 , wherein the removing of the dummy layer includes etching a portion of the source/drain epitaxial features below the dummy layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Lin Shih-Che
• Huang Po-Yu
• Wu Shih-Chieh
• Wu I-Wen
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/46

  comprising air gaps · CPC title