Cmp safe alignment mark

US2024387398A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024387398-A1
Application numberUS-202418787820-A
CountryUS
Kind codeA1
Filing dateJul 29, 2024
Priority dateSep 30, 2020
Publication dateNov 21, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.

First claim

Opening claim text (preview).

1 . A structure, comprising: a substrate including a surface; a recess in a first region of the surface; a first material in the recess, wherein the first material is different from a material of a first portion of the surface that surrounds the recess and the first material has been treated with an oxygen plasma; and a device structure in a second region of the surface of the substrate. 2 . The structure of claim 1 , comprising, wherein the first portion of the surface has been hardened. 3 . The structure of claim 1 , wherein the first material is silicon oxide. 4 . The structure of claim 1 , wherein the first material is silicon nitride. 5 . The structure of claim 1 , wherein the first layer is a polymer material. 6 . The structure of claim 1 , wherein the first material allows a laser light to pass through. 7 . The structure of claim 1 , comprising an isolation layer in the recess, wherein the first material is on the isolation layer. 8 . The structure of claim 7 , wherein the isolation layer is a dielectric material that is different from the first material. 9 . The structure of claim 1 , comprising a dielectric layer on the recess and the device structure, the dielectric layer is a different material from the first material. 10 . The structure of claim 1 , wherein the first portion is a semiconductor material. 11 . A structure, comprising: a substrate having a first surface; a first device structure on a first region of the first surface; an alignment mark on a second region of the first surface, the alignment mark including a filling material in a recess; and a dielectric layer directly on the alignment mark, a material composition of the filling material of the alignment mark being different from a material composition of the dielectric layer. 12 . The structure of claim 11 , wherein the filling material is silicon oxide. 13 . The structure of claim 11 , wherein the filling material is silicon nitride. 14 . The structure of claim 11 , wherein the filling material is a polymer material. 15 . The structure of claim 11 , wherein the filling material allows a laser light to pass through. 16 . The structure of claim 11 , wherein the alignment mark includes an isolation layer in the recess, and the filling material is on the isolation layer. 17 . The structure of claim 16 , wherein the isolation layer is a dielectric material that is different from the filling material. 18 . A structure, comprising: a substrate, a semiconductor layer on the substrate; a recess in a first region of the semiconductor layer; an isolation layer of a first dielectric material in the recess; and a second dielectric material in the recess and on the isolation layer, wherein the second dielectric material is an oxygen treated material. 19 . The structure of claim 18 , wherein the first layer is one or more of silicon oxide, silicon nitride, or a polymer material. 20 . The structure of claim 18 , wherein the first layer allows a laser light to pass through.

Assignees

Inventors

Classifications

  • involving a dielectric removal step · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

  • for alignment · CPC title

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Frequently asked questions

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What does patent US2024387398A1 cover?
The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W46/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 21 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).