Semiconductor devices and methods of formation

Patent metadata

Field	Value
Publication number	US-2024387381-A1
Application number	US-202418786849-A
Country	US
Kind code	A1
Filing date	Jul 29, 2024
Priority date	Mar 18, 2022
Publication date	Nov 21, 2024
Grant date	—

Abstract

Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first dielectric layer; a first conductive structure in the first dielectric layer; one or more second dielectric layers above the first dielectric layer and above the first conductive structure; a second conductive structure in the one or more second dielectric layers and over the first conductive structure; one or more metal liner layers between the second conductive structure and the one or more second dielectric layers; and a nitride barrier layer between the one or more metal liner layers and the one or more second dielectric layers,
wherein at least one metal liner layer of the one or more metal liner layers is electrically coupled with a top surface of the first conductive structure, and the second conductive structure is electrically coupled with the top surface of the first conductive structure through the at least one metal liner layer, or
wherein the second conductive structure is electrically coupled directly with the top surface of the first conductive structure.

2 . The semiconductor structure of claim 1 , wherein at least one metal liner layer of the one or more metal liner layers is directly electrically coupled with the top surface of the first conductive structure; and
wherein the one or more metal liner layers comprise at least one of:
a cobalt (Co) liner, or
a ruthenium (Ru) liner.

3 . The semiconductor structure of claim 1 , further comprising:
a capping layer over the second conductive structure,
wherein the capping layer comprises at least one of:
a cobalt (Co) capping layer, or
a ruthenium cobalt (RuCo) capping layer.

4 . The semiconductor structure of claim 1 , wherein the second conductive structure comprises copper (Cu); and
wherein the nitride barrier layer comprises a tantalum nitride (TaN) barrier layer that is configured to reduce diffusion of the copper from the second conductive structure.

5 . The semiconductor structure of claim 1 , wherein the at least one metal liner layer is electrically coupled directly with the top surface of the first conductive structure, and the second conductive structure is electrically coupled with the top surface of the first conductive structure through the at least one metal liner layer;
wherein the at least one metal liner layer comprises a single metal liner layer; and wherein a first thickness, of the single metal liner layer between the nitride barrier layer and the second conductive structure, is greater relative to a second thickness of the single metal liner layer between the first conductive structure and the second conductive structure.

6 . The semiconductor structure of claim 5 , wherein the second thickness is in a range of approximately 30% of the first thickness to approximately 80% of the first thickness.

7 . The semiconductor structure of claim 1 , wherein the at least one metal liner layer is electrically coupled directly with the top surface of the first conductive structure, and the second conductive structure is electrically coupled with the top surface of the first conductive structure through the at least one metal liner layer;
wherein the at least one metal liner layer comprises a first metal liner layer and a second metal liner layer of the one or more metal liner layers; and wherein a first thickness, of the first metal liner layer between the nitride barrier layer and the second conductive structure, is greater relative to a second thickness of first metal liner layer between the first conductive structure and the second conductive structure.

8 . The semiconductor structure of claim 7 , wherein the first metal liner layer is between the first conductive structure and the second metal liner layer; and
wherein the second metal liner layer is between the first metal liner layer and the second conductive structure.

9 . The semiconductor structure of claim 7 , wherein the first metal liner layer is between the second conductive structure and the second metal liner layer; and
wherein the second metal liner layer is between the first metal liner layer and the first conductive structure.

10 . A semiconductor structure, comprising:
a first dielectric layer; a first conductive structure in the first dielectric layer; an etch stop layer above the first dielectric layer and above the first conductive structure; a second dielectric layer above the etch stop layer and above the first conductive structure; a second conductive structure in the second dielectric layer and over the first conductive structure,
wherein the second conductive structure extends through the etch stop layer; and
a graphene layer between the first conductive structure and the etch stop layer,
wherein the second conductive structure extends through the graphene layer.

11 . The semiconductor structure of claim 10 , further comprising:
one or more metal liner layers between the second conductive structure and the second dielectric.

12 . The semiconductor structure of claim 11 , wherein at least one of the one or more metal liner layers extends through the graphene layer.

13 . The semiconductor structure of claim 11 , wherein the one or more metal liner layers comprise at least one of:
a cobalt (Co) liner, or a ruthenium (Ru) liner.

14 . The semiconductor structure of claim 10 , further comprising:
a metal interfacial layer between the graphene layer and the etch stop layer.

15 . The semiconductor structure of claim 14 , wherein the metal interfacial layer comprises a cobalt interfacial layer.

16 . A semiconductor structure, comprising:
a first dielectric layer; a first conductive structure in the first dielectric layer; an etch stop layer above the first dielectric layer and above the first conductive structure; a second dielectric layer above the etch stop layer and above the first conductive structure; a second conductive structure in the second dielectric layer and over the first conductive structure,
wherein the second conductive structure extends through the etch stop layer; and
a graphene barrier layer between the first conductive structure and the second conductive structure.

17 . The semiconductor structure of claim 16 , wherein the graphene barrier layer is further included on sidewalls of the second conductive structure.

18 . The semiconductor structure of claim 17 , wherein a thickness of the graphene barrier layer between the first conductive structure and the second conductive structure, is less than a thickness of the graphene barrier layer on the sidewalls of the second conductive structure.

19 . The semiconductor structure of claim 16 , wherein the graphene barrier layer comprises bilayer graphene.

20 . The semiconductor structure of claim 19 , wherein an inter-atom spacing of the bilayer graphene of the graphene barrier layer is less than an atomic diameter of a conductive material of the second conductive structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Chi Chih-Chien
• Peng Hsin-Ying
• Huang Jau-Jiun
• Lee Ya-Lien
• Chen Kuan-Chia
• Kuo Chia-Pang
• Liu Yao-Min

Classifications

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title