Multi version library cell handling and integrated circuit structures fabricated therefrom

Patent metadata

Field	Value
Publication number	US-2024362391-A1
Application number	US-202418769148-A
Country	US
Kind code	A1
Filing date	Jul 10, 2024
Priority date	Sep 20, 2017
Publication date	Oct 31, 2024
Grant date	—

Abstract

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

First claim

What is claimed is:

1 . A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction; forming a first version of a cell type over a first portion of the plurality of gate lines, the first version of the cell type comprising a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch; and forming a second version of the cell type over a second portion of the plurality of gate lines laterally adjacent to the first version of the cell type along the second direction, the second version of the cell type comprising a second plurality of interconnect lines having the second pitch along the second direction, and the second version of the cell type structurally different than the first version of the cell type.

2 . The method of claim 1 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.

3 . The method of claim 2 , wherein the first version of the cell type is a first version of an inverter cell.

4 . The method of claim 1 , wherein individual ones of the second plurality of interconnect lines of the second version of the cell type do not align with individual ones of the plurality of gate lines along the first direction at both edges of the second version of the cell type along the second direction.

5 . The method of claim 4 , wherein the second version of the cell type is a second version of an inverter cell.

6 . The method of claim 1 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at a first edge but not at a second edge of the first version of the cell type along the second direction.

7 . The method of claim 6 , wherein the first version of the cell type is a first version of a NAND cell.

8 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction;
a first version of a cell type over a first portion of the plurality of gate lines, the first version of the cell type comprising a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch; and
a second version of the cell type over a second portion of the plurality of gate lines laterally adjacent to the first version of the cell type along the second direction, the second version of the cell type comprising a second plurality of interconnect lines having the second pitch along the second direction, and the second version of the cell type structurally different than the first version of the cell type.

9 . The computing device of claim 8 , further comprising:
a memory coupled to the board.

10 . The computing device of claim 8 , further comprising:
a communication chip coupled to the board.

11 . The computing device of claim 8 , further comprising:
a battery coupled to the board.

12 . The computing device of claim 8 , further comprising:
a camera coupled to the board.

13 . The computing device of claim 8 , further comprising:
a display coupled to the board.

14 . The computing device of claim 8 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 8 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A library for a cell layout design, the library comprising:
a first version of a cell type for placement over a first portion of a plurality of gate lines, the first version of the cell type comprising a first plurality of interconnect lines; and a second version of the cell type for placement over a second portion of the plurality of gate lines, the second version of the cell type comprising a second plurality of interconnect lines, the second version of the cell type structurally different than the first version of the cell type.

17 . The library for the cell layout design of claim 16 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.

18 . The library for the cell layout design of claim 16 , wherein individual ones of the second plurality of interconnect lines of the second version of the cell type do not align with individual ones of the plurality of gate lines along the first direction at both edges of the second version of the cell type along the second direction.

19 . The library for the cell layout design of claim 16 , wherein individual ones of the interconnects of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at a first edge but not at a second edge of the first version of the cell type along the second direction.

20 . The library for the cell layout design of claim 16 , wherein individual ones of the interconnects of the second version of the cell type align with individual ones of the plurality of gate lines along the first direction at a second edge but not at a first edge of the second version of the cell type along the second direction.

Assignees

• Intel Corp

Inventors

• Kumar Ranjith
• Shi Quan
• Bohr Mark T
• Yeoh Andrew W
• Chakravarty Sourav
• Chappell Barbara A
• Webb M Clair

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D84/853

  comprising FinFETs · CPC title