Methods of dicing wafers having arrays of semiconductor chips therein and semiconductor chips formed thereby

Patent metadata

Field	Value
Publication number	US-2024355678-A1
Application number	US-202418636463-A
Country	US
Kind code	A1
Filing date	Apr 16, 2024
Priority date	Apr 19, 2023
Publication date	Oct 24, 2024
Grant date	—

Abstract

A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.

First claim

1 . A semiconductor chip, comprising:
an active layer on a top surface of an underlying base substrate, said active layer having: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers; and a protective layer covering at least a portion of a top surface of the active layer, which extends between the protective layer and the base substrate.

2 . The semiconductor chip of claim 1 , wherein a vertical level of a bottom of the chamfered edge is higher than a vertical level of the top surface of the base substrate.

3 . The semiconductor chip of claim 2 ,
wherein, in a region where the chamfered edge is not formed, a horizontal width of the active layer is equivalent to a horizontal width of the base substrate; and wherein, in a region where the chamfered edge is formed, a horizontal width of the active layer decreases in a direction away from the top surface of the base substrate.

4 . The semiconductor chip of claim 2 ,
wherein a horizontal width of the top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate.

5 . The semiconductor chip of claim 1 , wherein the base substrate further comprises a modifier formed along a side surface of the base substrate; and wherein the modifier is spaced apart from a bottom of the chamfered edge in a vertical direction.

6 . The semiconductor chip of claim 1 , wherein the top active layer and the bottom active layer are bonded to each other along the bonding surface by hybrid bonding.

7 . A semiconductor chip, comprising:
a base substrate; an active layer formed on a top surface of the base substrate; a protective layer covering at least a portion of a top surface of the active layer and being apart from the base substrate in a vertical direction with the active layer therebetween; and a first chamfer extending inside from the top surface of the active layer and formed along an edge of the top surface of the active layer; wherein the active layer includes a top active layer and a bottom active layer distinguished from each other with reference to a bonding surface extending between the top active layer and the bottom active layer; and wherein a vertical level of a bottom of the first chamfer is lower than a vertical level of the bonding surface in the active layer.

8 . The semiconductor chip of claim 7 ,
wherein the vertical level of the bottom of the first chamfer is higher than a vertical level of the top surface of the base substrate.

9 . The semiconductor chip of claim 8 ,
wherein, in a region in which the first chamfer is not formed, a horizontal width of the active layer is equivalent to a horizontal width of the base substrate; and wherein, in a region in which the first chamfer is formed, a horizontal width of the active layer decreases away from the base substrate.

10 . The semiconductor chip of claim 8 ,
wherein a side surface of the active layer comprises a top side surface, which define the first chamfer, and a bottom side surface; and wherein the top side surface of the active layer extends from an edge of the top surface of the active layer to an edge of the bottom side surface of the active layer.

11 . The semiconductor chip of claim 7 ,
wherein the base substrate comprises a second chamfer extending inside from a top surface; wherein the first chamfer completely passes through the active layer; and wherein the second chamfer communicates with the first chamfer.

12 . The semiconductor chip of claim 11 ,
wherein a horizontal width of a top surface of the active layer is about 15 μm to about 30 μm smaller than a horizontal width of a bottom surface of the base substrate; and wherein a horizontal width of a bottom surface of the active layer is about 0.5 μm to about 15 μm smaller than the horizontal width of the bottom surface of the base substrate.

13 .- 18 . (canceled)

19 . A method of dicing a wafer, comprising:
forming a trench along a partition due line of a wafer by concentrating a first laser beam onto a surface of the wafer and removing a portion of a protective layer and a portion of an active layer, wherein the wafer comprises a base substrate, the active layer formed on a surface of the base substrate and having a bonding surface therein, and the protective layer covering the active layer; and positioning, in the base substrate, a concentration point of a second laser beam having a wavelength transmitted through the wafer, and forming a modifier in the base substrate along the partition due line; and wherein during the forming of the trench, a portion on the partition due line is removed from the bonding surface of the active layer.

20 . The method of claim 19 , wherein, in the forming of the trench, a horizontal width of the trench decreases toward the base substrate.

21 . The method of claim 19 , wherein, in the forming of the trench, the first laser beam is repeatedly concentrated onto a top surface of the wafer along the partition due line until the trench has a preset thickness.

22 . The method of claim 19 , wherein, in the forming of the trench, a portion of the base substrate is removed along the partition due line.

23 . The method of claim 19 , wherein, in the forming of the trench, the first laser beam has an output from about 1 W to about 5 W.

24 . The method of claim 19 , wherein the forming of the trench is performed after the forming of the modifier.

25 . The method of claim 24 , further comprising aligning the modifier with a concentration point of the first laser beam, before the forming of the trench.

26 . The method of claim 19 ,
wherein the protective layer is apart from the base substrate with the active layer therebetween; wherein the active layer is divided into a top active layer and a bottom active layer with reference to the bonding surface; and wherein the top active layer is bonded to the bottom active layer in the bonding surface through hybrid bonding.

27 .- 37 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Junho
• Kweon Junyun
• Park Haemin
• Lee Kwangyong
• Kim Jesung
• Cho Dayoung

Classifications

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H01L2224/80896

  Electricity · mapped topic