Method for forming an ohmic contact on a wide-bandgap semiconductor device and wide-bandgap semiconductor device

Patent metadata

Field	Value
Publication number	US-2024222462-A1
Application number	US-202218554189-A
Country	US
Kind code	A1
Filing date	Mar 25, 2022
Priority date	Apr 6, 2021
Publication date	Jul 4, 2024
Grant date	—

Abstract

The present disclosure relates to a method for forming an ohmic contact on a wide-bandgap semiconductor device comprising: shallow implanting a dopant through a first surface of a wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region of a wide-bandgap semiconductor material, thermal treatment of the interface region comprising the implanted dopant at a temperature below 1100° C., and depositing a metal material on top of the at least one interface region to form at least one ohmic contact region.
The present disclosure further relates to a wide-bandgap semiconductor device comprising a semiconductor body or epitaxial layer comprising a wide-bandgap semiconductor material, at least one interface region which is doped and arranged within the wide-bandgap semiconductor material, and at least one ohmic contact region arranged on top of the at least one interface region.

First claim

1 . A method for forming an ohmic contact on a wide-bandgap semiconductor device, comprising:
shallow implanting a dopant through a first surface of the wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region in a wide-bandgap semiconductor material; rapid thermal processing of the at least one interface region comprising the implanted dopant at a temperature below 1100° C.; after rapid thermal processing of the at least one interface region, depositing a metal material on top of the at least one interface region to form at least one ohmic contact region; and optionally annealing the deposited metal material at an annealing temperature below 700° C.

2 . The method of claim 1 , wherein shallow implanting is performed with an implantation energy of less than 10 keV, in particular at or below 5 keV.

3 . The method of claim 1 , wherein rapid thermal processing is performed at a temperature of 1000° C. and/or for a duration of five minutes.

4 . The method of claim 1 , wherein the deposited metal material is annealed at an annealing temperature of 450° C., 550° C. or 700° C.

5 . The method of claim 1 , wherein at least one of
shallow implanting the dopant comprises implanting the dopant into the wide-bandgap semiconductor material ( 2 ) using a dose between 10 14 /cm 2 and 10 18 /cm 2 ; the wide-bandgap semiconductor material comprises silicon carbide; the deposited metal material forms at least one contact metal layer without chemically reacting with the wide-bandgap semiconductor material in the at least one interface region; or the at least one ohmic contact region formed by the deposited metal material is thicker than the at least one interface region.

6 . The method of claim 1 , wherein the first surface corresponds to a top surface of the wide-bandgap semiconductor device and the metal material is deposited on top of the at least one interface region to form the at least one ohmic contact region on the frontside of the wide-bandgap semiconductor device.

7 . The method of claim 1 , wherein, after forming the interface region, further processing steps are carried out for forming specific wide-bandgap semiconductor devices.

8 . The method of claim 1 , further comprising at least one of the following:
performing a front-side processing of the wide-bandgap semiconductor device before forming at least one of the at least one interface region or the at least one ohmic contact region; or forming at least one of an oxide layer or a passivation layer before depositing the metal material.

9 . The method of claim 1 , further comprising at least one of the following:
performing a backside processing of the wide-bandgap semiconductor device, wherein the backside processing includes a thermal treatment step, which results in the thermal treatment of the interface region; or forming at least one backside contact on a second surface of the semiconductor device, wherein forming the at least one backside contact includes an annealing step, which results in the thermal treatment of the interface region.

10 . The method of claim 1 , further comprising:
forming at least one trench structure within the wide-bandgap semiconductor material or forming a frontside structure on the first surface; and using the at least one trench structure or the frontside structure, respectively, to laterally self-align the at least one interface region and/or the at least one ohmic contact region.

11 . The method of claim 1 , further comprising:
etching the wide-bandgap semiconductor material to form at least one recess, wherein at least one of the at least one ohmic contact region or a frontside electrode layer formed on a third surface of the at least one contact region serves as an etching mask.

12 . A wide-bandgap semiconductor device ( 1 ) formed from a method for forming an ohmic contact on a wide-bandgap semiconductor device, comprising:
shallow implanting a dopant through a first surface of the wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region in a wide-bandgap semiconductor material; rapid thermal processing of the at least one interface region comprising the implanted dopant at a temperature below 1100° C.; after rapid thermal processing of the at least one interface region, depositing a metal material on top of the at least one interface region to form at least one ohmic contact region; and optionally annealing the deposited metal material at an annealing temperature below 700° C.

13 . A wide-bandgap semiconductor device, comprising:
a semiconductor body or an epitaxial layer comprising a wide-bandgap semiconductor material; at least one interface region, which is doped and arranged within a shallow implantation layer of the wide-bandgap semiconductor material, the at least one interface region having a first thickness corresponding to an implantation energy of less than 15 keV; and at least one ohmic contact region comprising more than 99% metal material arranged within a contact layer on top the at least one interface region, the at least one ohmic contact region having a second thickness greater than the first thickness.

14 . The wide-bandgap semiconductor device of claim 13 , wherein the first thickness corresponding to an implantation energy of less than 10 keV, in particular at or below 5 keV.

15 . The wide-bandgap semiconductor device of claim 13 , wherein the at least one interface region has a thickness of below 50 nm, in particular 25 nm, or below 10 nm.

16 . The wide-bandgap semiconductor device of claim 13 , wherein the least one ohmic contact region has a thickness (T 2 ) of 100 nm.

17 . The wide-bandgap semiconductor device of claim 13 , further comprising at least one active region arranged within the wide-bandgap semiconductor material, the at least one active region having a third thickness, wherein at least one of
the third thickness is greater than at least one of the first thickness or the second thickness; or the at least one doped interface region has a higher dopant concentration than the at least one active region; or a dopant material of the at least one active region differs from a dopant material of the at least one interface region.

18 . The wide-bandgap semiconductor device of claim 13 , wherein the least one ohmic contact region forms a frontside contact of the wide-bandgap semiconductor device.

19 . The wide-bandgap semiconductor device of claim 13 , wherein:
the wide-bandgap semiconductor device has a cell pitch in the range from 1.5 to 3 μm; and/or the wide-bandgap semiconductor device comprises a plurality of source and gate regions, and a widths of corresponding source and gate contacts range from 0.75 μm to 1.5 μm.

20 . The wide-bandgap semiconductor device of claim 13 , wherein the wide-bandgap semiconductor device is a trench device comprising a trench structure, and the at least one interface region and the at least one ohmic contact region are laterally adjacent to the at least one trench structure.

21 . The wide-bandgap semiconductor device of claim 20 , wherein the at least one trench structure comprises a buried gate, an insulation area arranged on top of the buried gate, and at least one vertical passivation layer arranged laterally between the insulation area and the at least one interface region.

22 . The wide-bandgap semiconductor device of claim 13 , wherein the w

Assignees

• Hitachi Energy Ltd

Inventors

• Sundaramoorthy Vinoth
• Knoll Lars
• Wirths Stephan

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/0115 Primary

  to silicon carbide · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/834

  further characterised by the dopants · CPC title