Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2024215245-A1
Application number	US-202418595737-A
Country	US
Kind code	A1
Filing date	Mar 5, 2024
Priority date	Jul 24, 2020
Publication date	Jun 27, 2024
Grant date	—

Abstract

A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first stacked structure including first gate electrodes sequentially stacked on a substrate; a first supporter layer disposed on the first stacked structure and divided by first cut patterns extending in a first direction, wherein each of the first cut patterns comprises first sub-cut patterns spaced apart from each other in a second direction intersecting the first direction; a second stacked structure including second gate electrodes sequentially stacked on the first supporter layer; a second supporter layer disposed on the second stacked structure and divided by second cut patterns extending in the first direction, wherein each of the second cut patterns comprises second sub-cut patterns spaced apart from each other in the second direction; a third stacked structure including third gate electrodes sequentially stacked on the second supporter layer; a third supporter layer disposed on the third stacked structure and divided by third cut patterns extending in the first direction, wherein each of the third cut patterns comprises third sub-cut patterns spaced apart from each other in the second direction; and a channel structure penetrating the first stacked structure, the first supporter layer, the second stacked structure, the second supporter layer and the third stacked structure, wherein at least one of a ratio of the first cut patterns of the first supporter layer, a ratio of the second cut patterns of the second supporter layer and a ratio of the third cut patterns of the third supporter layer is different from each other.

2 . The semiconductor memory device of claim 1 , wherein the ratio of the first cut patterns of the first supporter layer, the ratio of the second cut patterns of the second supporter layer and the ratio of the third cut patterns of the third supporter layer is different from each other.

3 . The semiconductor memory device of claim 1 , wherein the ratio of the second cut patterns of the second supporter layer is greater than the ratio of the third cut patterns of the third supporter layer and is less than the ratio of the first cut patterns of the first supporter layer.

4 . The semiconductor memory device of claim 1 , wherein the ratio of the second cut patterns of the second supporter layer is less than the ratio of the third cut patterns of the third supporter layer and is greater than the ratio of the first cut patterns of the first supporter layer.

5 . The semiconductor memory device of claim 1 , wherein the ratio of the second cut patterns of the second supporter layer is less than the ratio of the first cut patterns of the first supporter layer and the ratio of the third cut patterns of the third supporter layer.

6 . The semiconductor memory device of claim 1 , wherein side walls of the channel structure have steps at an interface between the first stacked structure and the first supporter layer and an interface between the second stacked structure and the second supporter layer.

7 . The semiconductor memory device of claim 1 , wherein the third supporter layer include a material different from the first supporter layer and the second supporter layer.

8 . The semiconductor memory device of claim 1 , further comprising:
a fourth stacked structure including fourth gate electrodes sequentially stacked on the third supporter layer; and a fourth supporter layer disposed on the fourth stacked structure and divided fourth cut patterns, and wherein each of the fourth cut patterns comprises fourth sub-cut patterns spaced apart from each other in the second direction, and a ratio of the fourth cut patterns of the fourth supporter layer is different from at least one of the ratio of the first cut patterns of the first supporter layer, the ratio of the second cut patterns of the second supporter layer and the ratio of the third cut patterns of the third supporter layer.

9 . The semiconductor memory device of claim 8 , wherein the fourth supporter layer include a material different from the first supporter layer, the second supporter layer, the third supporter layer and a fourth supporter layer.

10 . The semiconductor memory device of claim 1 , further comprising:
a block cut structure cutting at least one of the second stacked structure or the first stacked structure.

11 . A semiconductor memory device comprising:
a peripheral logic structure, and a cell array structure on the peripheral logic structure; wherein the cell array structure includes:
a first substrate,
a first stacked structure including first gate electrodes and first insulating layers alternately stacked on the first substrate,
a first supporter layer disposed on the first stacked structure and divided by first cut patterns extending in a first direction,
a second stacked structure including second gate electrodes and second insulating layers alternately stacked on the first supporter layer,
a second supporter layer disposed on the second stacked structure and divided by second cut patterns extending in the first direction,
a channel structure penetrating the first stacked structure, the first supporter layer and the second stacked structure,
a first metal layer on the second supporter layer, and
a first bonding metal on the first metal layer,
the peripheral logic structure includes:
a second substrate,
a second metal layer on the second substrate, and
a second bonding metal on the second metal layer,
the first bonding metal is connected to the second bonding metal, each of the first cut patterns comprises first sub-cut patterns spaced apart from each other in a second direction intersecting the first direction, each of the second cut patterns comprises second sub-cut patterns spaced apart from each other in the second direction, and a ratio of the first cut patterns of the first supporter layer is different from a ratio of the second cut patterns of the second supporter layer.

12 . The semiconductor memory device of claim 11 , wherein the ratio of the first cut patterns of the first supporter layer is less from the ratio of the second cut patterns of the second supporter layer.

13 . The semiconductor memory device of claim 11 , wherein the second supporter layer include a material different from the first supporter layer.

14 . The semiconductor memory device of claim 11 , further comprising:
a block cut structure cutting at least one of the second stacked structure or the first stacked structure, and wherein at least part of the block cut structure overlaps at least one of the first cut patterns and the second cut patterns.

15 . A semiconductor memory device comprising:
a first stacked structure including first gate electrodes and first insulating layers alternately stacked on a substrate; a first supporter layer disposed on the first stacked structure and divided by first cut patterns extending in a first direction, wherein each of the first cut patterns comprises first sub-cut patterns spaced apart from each other in a second direction intersecting the first direction; a second stacked structure including second gate electrodes and second insulating layers alternately stacked on the first supporter layer; a second supporter layer disposed on the second stacked structure and divided by second cut patterns extending in the first direction, wherein each of the second cut patterns comprises second sub-cut patterns spaced apart from each other in the second direction; a block cut structure including at least one of a first sub-cut structure cutting the first stacked structure, a second sub

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji Young
• Yang Woo Sung
• Hwang Sung-Min
• Sung Suk Kang
• Lim Joon-Sung

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title