Process for thin film capacitor integration

Patent metadata

Field	Value
Publication number	US-2024194574-A1
Application number	US-202418585629-A
Country	US
Kind code	A1
Filing date	Feb 23, 2024
Priority date	May 19, 2021
Publication date	Jun 13, 2024
Grant date	—

Abstract

Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
a first conductor disposed on a substrate; a second conductor disposed on the substrate and running parallel to the first conductor with a spacing between the first and second conductors; a first insulator having first and second surfaces opposite each other, wherein a first portion of the first surface is disposed on the substrate, and a second portion of the first surface is disposed on the first conductor; a second insulator having first and second surfaces opposite each other, wherein respective portions of the first surface are disposed on the first conductor, the substrate, and the second conductor, respectively; a third insulator having first and second surfaces opposite each other, wherein respective portions of the first surface are disposed on the second conductor, and on the substrate, respectively; a metal pillar on the second surface of the first conductor; and a conductive adhesive disposed on the second surface of the second conductor.

2 . The IC of claim 1 , further comprising:
a lead frame having first and second leads, wherein the first lead is coupled to the first conductor; and a capacitor having first and second capacitor terminals, the first capacitor terminal connected to the second lead using conductive adhesive, and the second capacitor terminal connected to the second conductor.

3 . The IC of claim 1 , wherein the metal pillar includes copper.

4 . The IC of claim 1 , wherein the first and second insulators include polyimide.

5 . The IC of claim 2 , wherein the IC is packaged in a flip chip package.

6 . The IC of claim 2 , wherein the first lead is electrically connected to the substrate through the first conductor, the metal pillar and conductive adhesive.

7 . The IC of claim 1 , further comprising:
a lead frame having first, second and third leads, wherein the first lead is coupled to the first conductor; and a capacitor having first and second capacitor terminals, wherein the first capacitor terminal is connected to the second lead using conductive adhesive, and the second capacitor terminal is connected to the third lead using conductive adhesive.

8 . The IC of claim 7 , wherein the capacitor is not electrically connected to the substrate.

9 . An integrated circuit (IC) comprising:
first and second conductors disposed on a substrate; a first insulator having first and second surfaces opposite each other, wherein a first portion of the first surface is disposed on the substrate, and a second portion of the first surface is disposed on the first conductor; a second insulator having first and second surfaces opposite each other, wherein respective portions of the first surface are disposed on the first conductor, the substrate, and the second conductor, respectively; a third insulator having first and second surfaces opposite each other, wherein respective portions of the first surface are disposed on the second surface of the second conductor, and the substrate, respectively; a first metal pillar disposed on the second surface of the first conductor, extending beyond the first and second insulators; a second metal pillar disposed on the second surface of the second conductor, extending beyond the second and third insulators; a capacitor having first and second capacitor terminals, wherein the first capacitor terminal is coupled to the substrate; and a lead frame having first and second leads, wherein the first and second leads are connected to the first and second metal pillars, respectively.

10 . The IC of claim 9 , further comprising:
third and fourth leads on the lead frame; and a conductive clip having first and second clip end connections, wherein the first and second clip end connections are connected to the third and fourth leads, respectively, and the conductive clip is electrically connected to the second capacitor terminal.

11 . The IC of claim 10 , wherein the conductive clip provides an electrical connection between the third and fourth leads and the second capacitor terminal.

12 . The IC of claim 10 , wherein the capacitor is electrically connected between the substrate and the third and fourth leads.

13 . The IC of claim 10 , wherein the capacitor is bonded to the conductive clip using conductive adhesive.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Ramadass Yogesh Kumar
• Pavone Salvatore Frank
• Chowdhury Mahmud Halim

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title