Memory device and method of forming the same

Patent metadata

Field	Value
Publication number	US-2024188290-A1
Application number	US-202218082048-A
Country	US
Kind code	A1
Filing date	Dec 15, 2022
Priority date	Dec 1, 2022
Publication date	Jun 6, 2024
Grant date	—

Abstract

Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

First claim

What is claimed is:

1 . A memory device comprising:
a stack structure; and a plurality of gate line slit (GLS) structures vertically extending through the stack structure, to divide the stack structure into a plurality of stack portions, wherein
the plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction;
each stack portion is between corresponding adjacent GLS structures; and
at least one edge stack portion, along the second direction, of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

2 . The memory device according to claim 1 , wherein the at least one edge stack portion is configured with at least a dimension, a shape, and/or a component different from the non-edge stack portion of the stack structure and defined by corresponding adjacent GLS structures at the edge of the stack structure.

3 . The memory device according to claim 2 , wherein the at least one edge stack portion is configured having a width in the second direction, between the corresponding adjacent GLS structures at the edge of the stack structure, larger than the non-edge stack portion of the stack structure.

4 . The memory device according to claim 3 , wherein the width of the at least one edge stack portion in the second direction is at least 1.5 times larger than a width of the non-edge stack portion of the stack structure in the second direction.

5 . The memory device according to claim 2 , wherein the at least one edge stack portion is configured having one or more convex structures each protruding toward an adjacent GLS structure at the edge of the stack structure, wherein the one or more convex structures have a shape of a square wave, a pulse wave, a sine wave, a sawtooth, a triangle wave, or a combination thereof.

6 . The memory device according to claim 2 , wherein the at least one edge stack portion at the edge of the stack structure further comprises one or more sub-GLS structures vertically through the at least one edge stack portion of the stack structure.

7 . The memory device according to claim 6 , wherein the one or more sub-GLS structures discretely extend along the first direction inside the at least one edge stack portion.

8 . The memory device according to claim 7 , wherein a width of the at least one edge stack portion comprising the one or more sub-GLS structures is at least double a width of the non-edge stack portion of the stack structure in the second direction.

9 . The memory device according to claim 2 , wherein
the plurality of stack portions includes two edge stack portions that are configured differently with one another in the dimension, the shape, and/or the component, and the two edge stack portions are configured differently from the non-edge stack portion of the plurality of stack portions.

10 . The memory device according to claim 1 , wherein
the stack structure comprises alternating conductor/dielectric layer pairs.

11 . The memory device according to claim 1 , wherein
the non-edge stack portion of the stack structure comprises a channel structure or a word line contact plug, and the at least one edge stack portion of the stack structure is devoid of a channel structure or a word line contact plug.

12 . A memory device comprising:
a memory plane comprising:
memory blocks and gate line slit (GLS) structures extending vertically through the memory blocks, wherein
the GLS structures extend along a first direction and are arranged along a second direction substantially perpendicular to the first direction; and
at least one edge block, along the second direction, of the memory plane between an edge GLS structure and an adjacent GLS structure includes a configuration different from a non-edge block of the memory plane along the second direction.

13 . The memory device according to claim 12 , wherein the at least one edge block is configured with at least a dimension, a shape, and/or a component different from the non-edge block of the memory plane.

14 . The memory device according to claim 13 , wherein
the at least one edge block comprises:
a width at least 1.5 times larger than a width of the non-edge block in the second direction,
a shape comprising square wave, pulse wave, sine wave, sawtooth, triangle wave, or a combination thereof, and/or
one or more sub-GLS structures vertically through the at least one edge block.

15 . The memory device according to claim 12 , wherein
the non-edge block comprises a channel structure or a word line contact plug, and the at least one edge block is devoid of a channel structure or a word line contact plug.

16 . A method for forming a memory device, comprising:
forming an alternating dielectric stack; forming a plurality of gate line slits (GLSs) extending vertically through the alternating dielectric stack to divide the alternating dielectric stack into a plurality of dielectric-stack portions, wherein
the plurality of GLSs extend along a first direction and are arranged along a second direction substantially perpendicular to the first direction;
each dielectric-stack portion is formed between corresponding adjacent GLSs; and
the plurality of GLSs is formed in a manner such that at least one edge dielectric-stack portion along the second direction includes a configuration different from a non-edge dielectric-stack portion of the plurality of dielectric-stack portions along the second direction.

17 . The method according to claim 16 , further comprising:
forming a plurality of stack portions by replacing a dielectric layer of the alternating dielectric stack with a conductor layer, wherein at least one edge stack portion of the plurality of stack portions includes a configuration different from a non-edge stack portion, and forming the plurality of GLSs by forming a material in the plurality of GLSs.

18 . The method according to claim 16 , wherein
the plurality of GLSs are formed in a manner such that the at least one edge dielectric-stack portion is configured with at least a dimension, a shape, and/or a component different from the non-edge dielectric-stack portion.

19 . The method according to claim 18 , wherein
the at least one edge dielectric-stack portion comprises:
a width, in the second direction, that is at least 1.5 times larger than a width of the non-edge dielectric-stack portion in the second direction,
a shape comprising a square wave, pulse wave, sine wave, sawtooth, triangle wave, or a combination thereof, along a lateral plane, and/or
one or more sub-GLS structures vertically through the at least one edge dielectric-stack portion.

20 . The method according to claim 16 , further comprising:
before forming the plurality of GLSs, determining a width of the at least one edge dielectric-stack portion based on:
a height of the alternating dielectric stack over the semiconductor layer,
a surface tension and a contact angle of a liquid applied for forming the plurality of GLSs, and/or
a width of each GLS.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xie Wei
• Fan Dongyu
• Wang Di
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/697 Primary

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title