Method of Operating a PVD Apparatus

Patent metadata

Field	Value
Publication number	US-2024177997-A1
Application number	US-202318244904-A
Country	US
Kind code	A1
Filing date	Sep 11, 2023
Priority date	Nov 25, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

A PVD apparatus can perform a cleaning step and a deposition step on an electrically conductive feature formed on a semiconductor substrate. The semiconductor substrate with the electrically conductive feature thereon can be positioned on the substrate support. A cleaning step can be performed to remove material from the electrically conductive feature predominantly by etching with ions of an inert gas while the target is simultaneously sputtered. A deposition step is performed by applying no RF bias to the substrate support or applying an RF bias which is less than the RF bias applied to the substrate support during the cleaning step and supplying an electrical signal having an associated electrical power to the target. The RF bias, if present, and electrical power are sufficient to deposit an electrically conductive deposition material onto the electrically conductive feature by PVD.

First claim

1 . A method of operating a PVD apparatus to perform a cleaning step and a deposition step on an electrically conductive feature formed on a semiconductor substrate comprising the steps of:
providing a PVD apparatus comprising a chamber having a substrate support, a target, an RF bias signal supply for applying an RF bias to the substrate support and an electrical signal supply for supplying an electrical signal to the target; positioning the semiconductor substrate with the electrically conductive feature thereon on the substrate support; performing a cleaning step by introducing at least one inert gas into the chamber, applying an RF bias to the substrate support and supplying an electrical signal having an associated electrical power to the target, wherein the RF bias and electrical power are sufficient to remove material from the electrically conductive feature predominantly by etching with ions of the inert gas while the target is simultaneously sputtered; and performing a deposition step by applying no RF bias to the substrate support or applying an RF bias which is less than the RF bias applied to the substrate support during the cleaning step and supplying an electrical signal having an associated electrical power to the target, wherein the RF bias, if present, and electrical power are sufficient to deposit an electrically conductive deposition material onto the electrically conductive feature by PVD.

2 . The method according to claim 1 , wherein the substrate support is at a first position during the cleaning step and at a second position during the deposition step, wherein the second position is closer to the target than the first position.

3 . The method according to claim 2 , wherein the first position of the substrate support corresponds to a target to semiconductor substrate separation of greater than 100 mm.

4 . The method according to claim 2 , wherein the second position of the substrate support corresponds to a target to semiconductor substrate separation of less than 75 mm.

5 . The method according to claim 1 , wherein the electrical power to the target used during the deposition step is greater than the electrical power used during the cleaning step.

6 . The method according to claim 5 , wherein the electrical signal supplied to the target is a DC electrical signal.

7 . The method according to claim 1 , wherein the electrical power to the target used during the cleaning step is less than 500 W.

8 . The method according to claim 1 , wherein the electrical power to the target used during the deposition step is greater than 1000 W.

9 . The method according to claim 1 , wherein the RF bias applied to the substrate support during the cleaning step results in a DC bias being applied to the semiconductor substrate, wherein the DC bias is greater than 70 V.

10 . The method according to claim 1 , wherein the RF bias applied to the substrate support during the cleaning step or the lack thereof results in a DC bias being applied to the semiconductor substrate, wherein the DC bias is less than 25 V.

11 . The method according to claim 1 , wherein the inert gas is Argon.

12 . The method according to claim 1 , wherein the material which is removed from the electrically conductive feature is an oxide of a material that the electrically conductive feature is formed from.

13 . The method according to claim 12 , wherein the electrically conductive feature is formed from aluminium and the material which is removed from the electrically conductive feature is aluminium oxide.

14 . The method according to claim 13 , wherein the aluminium electrically conductive feature is a bond pad for the semiconductor substrate.

15 . The method according to claim 12 , wherein the electrically conductive feature is formed from aluminium alloy.

16 . The method according to claim 1 , wherein the electrically conductive feature is formed from copper and the material which is removed from the copper electrically conductive feature is one or more of titanium, tantalum, a nitride of titanium or a nitride of tantalum.

17 . The method according to claim 1 , wherein the electrically conductive deposition material deposited onto the electrically conductive feature is titanium.

18 . The method according to claim 1 , wherein the deposition of the electrically conductive deposition material onto the electrically conductive feature is part of an Under Bump Metallization (UBM) process.

19 . A PVD apparatus for performing a cleaning step and a deposition step on an electrically conductive feature formed on a semiconductor substrate in accordance with the method of claim 1 , the PVD apparatus comprising:
the chamber having the substrate support; the target; the RF bias signal supply for applying the RF bias to the substrate support; the electrical signal supply for supplying the electrical signal to the target; and a controller, wherein the controller is configured to control positioning the semiconductor substrate, performing the cleaning step, and performing the deposition step.

20 . The PVD apparatus according to claim 19 , wherein the controller is configured to maintain the substrate support at a first position during the cleaning step and at a second position during the deposition step, wherein the second position is closer to the target than the first position.

Assignees

• Spts Technologies Ltd

Inventors

• Haymore Scott
• Wilby Tony
• Burgess Steve

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title