Semiconductor package device

Patent metadata

Field	Value
Publication number	US-2024170385-A1
Application number	US-202218145198-A
Country	US
Kind code	A1
Filing date	Dec 22, 2022
Priority date	Nov 17, 2022
Publication date	May 23, 2024
Grant date	—

Abstract

A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

First claim

What is claimed is:

1 . A semiconductor package device, comprising:
a chip; and a redistribution layer disposed corresponding to the chip and electrically connected to the chip, wherein the redistribution layer comprises a plurality of first metal lines and a plurality of second metal lines, wherein, from a top view, at least one of the second metal lines is disposed between two adjacent first metal lines, an included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees, and a first width of one of the two adjacent first metal lines is greater than a second width of the at least one of the second metal lines.

2 . The semiconductor package device as claimed in claim 1 , wherein the first metal lines comprise ground routings.

3 . The semiconductor package device as claimed in claim 1 , wherein the first width is greater than or equal to twice the second width.

4 . The semiconductor package device as claimed in claim 1 , wherein the at least one of the second metal lines is electrically connected to the chip.

5 . The semiconductor package device as claimed in claim 1 , wherein one of the two adjacent first metal lines has a first portion and a second portion, the second portion connects to the first portion, the first portion overlaps the chip, and the first portion and the second portion have different widths.

6 . The semiconductor package device as claimed in claim 1 , further comprising a protective layer surrounding the chip.

7 . The semiconductor package device as claimed in claim 6 , wherein the protective layer contacts at least two sides of the chip.

8 . The semiconductor package device as claimed in claim 1 , further comprising a plurality of bonding pads corresponding to terminals of the first metal lines and the second metal lines, and a distance between two adjacent bonding pads is greater than or equal to 4 times the first width and less than or equal to 8 times the first width.

9 . The semiconductor package device as claimed in claim 1 , wherein a distance between the at least one of the second metal lines and one of the two adjacent first metal lines is greater than or equal to twice the second width.

10 . The semiconductor package device as claimed in claim 6 , wherein the at least one of the second metal lines and the two adjacent first metal lines straddle between the chip and the protective layer.

11 . The semiconductor package device as claimed in claim 1 , wherein the first metal lines comprise dummy structures.

12 . The semiconductor package device as claimed in claim 3 , wherein the first width is greater than or equal to twice the second width and less than or equal to three times the second width.

13 . The semiconductor package device as claimed in claim 9 , wherein the distance between the at least one of the second metal lines and the one of the two adjacent first metal lines is greater than or equal to twice the second width and less than or equal to three times the second width.

14 . The semiconductor package device as claimed in claim 1 , wherein a length of one of the two adjacent first metal lines is greater than or equal to 16 times the second width.

15 . The semiconductor package device as claimed in claim 14 , wherein the length of one of the two adjacent first metal lines is greater than or equal to 16 times the second width and less than or equal to 20 times the second width.

16 . The semiconductor package device as claimed in claim 1 , wherein the second metal lines comprise signal routings.

17 . The semiconductor package device as claimed in claim 6 , wherein the protective layer comprises epoxy molding compound (EMC).

18 . The semiconductor package device as claimed in claim 8 , further comprising a plurality of bumps disposed on the redistribution layer.

19 . The semiconductor package device as claimed in claim 18 , further comprising an electronic component electrically connected to the chip through the redistribution layer, the bumps and the bonding pads.

20 . The semiconductor package device as claimed in claim 19 , wherein the electronic component comprises a printed circuit board (PCB), resistive components, capacitive components, inductive components, antenna components, circuit components or drive circuit components.

Assignees

• Innolux Corp

Inventors

• Lin Te-Hsun
• Liao Wen-Hsiang
• Chen Mei-Yen
• Shih Ming-Hsien
• Chen Yung-Feng
• Wang Cheng-Chi

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title