Semiconductor chip, debug system, and synchronization method

Patent metadata

Field	Value
Publication number	US-2024168861-A1
Application number	US-202318482241-A
Country	US
Kind code	A1
Filing date	Oct 6, 2023
Priority date	Nov 21, 2022
Publication date	May 23, 2024
Grant date	—

Abstract

A semiconductor chip includes a first common marker generating circuit and a second common marker generating circuit. The first common marker generating circuit is configured to send a first request signal to the second common marker generating circuit, the first request signal requesting a common marker to be sent to a second trace memory, and to send the common marker to a first trace memory, when a second request signal is received from the second common marker generating circuit, the second request signal requesting the common marker to be sent to the first trace memory. The second common marker generating circuit is configured to send the common marker to the second trace memory and to send the second request signal to the first common marker generating circuit, if a second core is running a user program at a time when the first request signal is received.

First claim

What is claimed is:

1 . A semiconductor chip comprising:
a first common marker generating circuit configured to send a common marker to a first trace memory configured to store trace data from a first core, the common marker allowing to synchronize the trace data from the first core with trace data from a second core different in type from the first core; and a second common marker generating circuit configured to send the common marker to a second trace memory configured to store the trace data from the second core, wherein the first common marker generating circuit is configured to:
send a first request signal to the second common marker generating circuit, the first request signal requesting the common marker to be sent to the second trace memory, when the first core is running a user program; and
send the common marker to the first trace memory, when a second request signal is received from the second common marker generating circuit, the second request signal requesting the common marker to be sent to the first trace memory, and
wherein the second common marker generating circuit is configured to send the common marker to the second trace memory and send the second request signal to the first common marker generating circuit, if the second core is running a user program at a time when the first request signal is received.

2 . The semiconductor chip according to claim 1 ,
wherein the first common marker generating circuit is configured to send the first request signal at regular intervals while the first core is running a user program.

3 . The semiconductor chip according to claim 2 ,
wherein the first common marker generating circuit includes:
a first counter configured to start counting when a first core starts to run a user program; and
a counter setting register in which a counter value is set, and
wherein the first common marker generating circuit is configured to send the first request signal if a counter value of the first counter matches a counter value set in the counter setting register.

4 . The semiconductor chip according to claim 3 , further comprising a clock selection circuit configured to select a clock, which is to be input to the first counter, from among a plurality of clocks.

5 . The semiconductor chip according to claim 3 ,
wherein a memory size of the first trace memory and a memory size of the second trace memory are different from each other.

6 . A debug system comprising:
the semiconductor chip according to claim 1 ; and a host computer configured to display the trace data from the first core and the trace data from the second core in synchronization based on the common marker.

7 . The debug system according to claim 6 ,
wherein the host computer is configured to display a screen on which a first graph indicating running time of a function on the first core and a second graph indicating running time of a function on the second core are synchronized based on the common marker.

8 . A synchronization method using a semiconductor chip which includes a first common marker generating circuit configured to send a common marker to a first trace memory configured to store trace data from a first core, and a second common marker generating circuit configured to send the common marker to a second trace memory configured to store trace data from a second core, wherein the common marker allows to synchronize the trace data from the first core with the trace data from the second core different in type from the first core, the synchronization method comprising:
a step of, when the first core is running a user program, sending a first request signal from the first common marker generating circuit to the second common marker generating circuit, the first request signal requesting the common marker to be sent to the second trace memory; a step of, if the second core is running a user program at a time when the second common marker generating circuit receives the first request signal, sending a second request signal from the second common marker generating circuit to the first common marker generating circuit, the second request signal requesting the common marker to be sent to the first trace memory, and sending the common marker from the second common marker generating circuit to the second trace memory; and a step of, when the first common marker generating circuit receives the second request signal, sending the common marker from the first common marker generating circuit to the first trace memory.

9 . The synchronization method according to claim 8 , further comprising a step of displaying the trace data from the first core and the trace data from the second core in synchronization based on the common marker.

Assignees

• Renesas Electronics Corp

Inventors

• Sasaki Hiroyuki
• Hatahara Hirofumi

Classifications

• G06F11/348 Primary

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/323 Primary

  Visualisation of programs or trace data · CPC title

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title