Semiconductor device, control system, and synchronization method

Patent metadata

Field	Value
Publication number	US-10243568-B2
Application number	US-201715797033-A
Country	US
Kind code	B2
Filing date	Oct 30, 2017
Priority date	Dec 5, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2 , a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is set, a comparison circuit 5 configured to compare the count value in the counter 3 with the set value in the periodic register 4 , a match flag register 6 in which a predetermined value is set when the count value coincides with the set value, a match output terminal 7 configured to output the value in the match flag register 6 from the own semiconductor device, a match input terminal 8 to which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counter 3 and the match flag register 6 when both the value in the match flag register 6 of the own semiconductor device and the value input to the match input terminal 8 become a predetermined value.

First claim

What is claimed is:

1. A semiconductor device comprising:
a clock oscillator;
a first counter configured to count the number of clocks generated by the clock oscillator;
a periodic register in which a value corresponding to a period for synchronization is set;
a first comparison circuit configured to compare the count value in the first counter with the set value in the periodic register;
a match flag register in which a first predetermined value is set when the count value in the first counter coincides with the set value in the periodic register;
a match output terminal configured to output the value in the match flag register;
a match input terminal to which a match signal value output from another semiconductor device to be synchronized is input; and
a reset circuit configured to reset the first counter and the match flag register when both the value in the match flag register and the match signal value and the match signal value input to the match input terminal become the first predetermined value.

2. The semiconductor device according to claim 1 , further comprising:
a limiting value register in which a limiting value of the number of clocks counted by the first counter is set;
a second comparison circuit configured to compare the count value in the first counter with the limiting value in the limiting value register; and
an overflow flag register in which a second predetermined value is set when the count value in the first counter coincides with the limiting value in the limiting value register,
wherein the reset circuit resets the first counter and the match flag register at a timing when both the value in the match flag register and the match signal value input from the match input terminal have become the first predetermined value in a state in which the value in the overflow flag register is a value other than the second predetermined value, a timing when the value in the overflow flag register has become the second predetermined value, and a timing when the value in the match flag register has become the first predetermined value in a state in which the value in the overflow flag register is the second predetermined value.

3. The semiconductor device according to claim 2 , wherein the semiconductor device outputs an interruption request when the count value in the first counter coincides with the limiting value in the limiting value register.

4. The semiconductor device according to claim 2 , wherein the overflow flag register is reset when the match signal value input from the match input terminal becomes the first predetermined value.

5. The semiconductor device according to claim 1 , further comprising a compare match timer configured to include a second counter and output an interruption request when the count value in the second counter coincides with a predetermined value,
wherein the reset circuit resets the first counter, the match flag register, and the second counter when both the value in the match flag register and the match signal value input to the match input terminal become the first predetermined value.

6. The semiconductor device according to claim 1 , further comprising a compare match timer configured to output an interruption request when the count value in the first counter coincides with a predetermined value.

7. The semiconductor device according to claim 1 , further comprising a control signal generation circuit configured to include a third counter and generate a control signal using the count value in the third counter,
wherein the reset circuit resets the first counter, the match flag register, and the third counter when both the value in the match flag register and the match signal value input to the match input terminal become the first predetermined value.

8. The semiconductor device according to claim 1 , further comprising a control signal generation circuit configured to generate a control signal using the count value in the first counter.

9. A control system comprising:
a first semiconductor device;
a second semiconductor device,
wherein
the first semiconductor device and the second semiconductor device each comprise:
a clock oscillator;
a counter configured to count the number of clocks generated by the clock oscillator;
a periodic register in which a value corresponding to a period for synchronization with a counterpart semiconductor device is set;
a first comparison circuit configured to compare the count value in the counter with the set value in the periodic register;
a match flag register in which a first predetermined value is set when the count value in the counter coincides with the set value in the periodic register;
a match output terminal configured to output the value in the match flag register from the own semiconductor device;
a match input terminal configured to receive the value in the match flag register of the counterpart semiconductor device output from the match output terminal of the counterpart semiconductor device;
a reset circuit configured to reset the counter and the match flag register when both the value in the match flag register of the own semiconductor device and the value input from the match input terminal become the first predetermined value; and
a control signal generation circuit configured to generate a control signal based on the count value in the counter or a count value in another counter reset at a timing the same as the timing when the counter is reset.

10. The control system according to claim 9 , wherein each of the first semiconductor device and the second semiconductor device further comprises:
a limiting value register in which a limiting value of the number of clocks counted by the counter is set;
a second comparison circuit configured to compare the count value in the counter and the limiting value in the limiting value register; and
an overflow flag register in which a second predetermined value is set when the count value in the counter coincides with the limiting value in the limiting value register,
wherein the reset circuit resets the counter and the match flag register at a timing when both the value in the match flag register of the own semiconductor device and the value input from the match input terminal have become the first predetermined value in a state in which the value in the overflow flag register is a value other than the second predetermined value, a timing when the value in the overflow flag register has become the second predetermined value, and a timing when the value in the match flag register of the own semiconductor device has become the first predetermined value in a state in which the value in the overflow flag register is the second predetermined value.

11. The control system according to claim 10 , further comprising:
a first driving circuit configured to drive an actuator; and
a second driving circuit configured to drive the actuator,
wherein,
the control signal generation circuit of the first semiconductor device generates a control signal for the first driving circuit, and
the control signal generation circuit of the second semiconductor device generates a control signal for the second driving circuit.

12. The control system according to claim 9 , further comprising:
a first driving circuit configured to drive an actuator; and
a second driving circuit configured to drive the actuator,
wherein,
the control signal generation circuit of the first semiconductor device generates a control signal for the first driving circuit, and
the control signal generation circuit of the second semiconductor device generates a control signal for the second driving circuit.

13. A synchronizat

Assignees

• Renesas Electronics Corp

Inventors

• Yamada Hiromichi
• Yamate Akihiro
• Suzuki Hitoshi
• Yuyama Yoichi
• Hirotsu Teppei

Classifications

• H03K21/406 Primary

  Synchronisation of counters · CPC title

• H03K21/38

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title