Metal wiring manufacturing method, transistor manufacturing method, and metal wiring

Patent metadata

Field	Value
Publication number	US-2024164012-A1
Application number	US-202418422164-A
Country	US
Kind code	A1
Filing date	Jan 25, 2024
Priority date	Jul 30, 2021
Publication date	May 16, 2024
Grant date	—

Abstract

Provided is a method of manufacturing a metal wiring on a substrate, including the steps of: forming a first layer containing a first material in at least part on the substrate; forming a crack in the first layer to form the first layer having the crack; and forming a second layer containing a second material in the first layer having the crack.

First claim

1 - 28 . (canceled)

29 . A wiring, comprising:
a first layer over a substrate, the first layer containing a first material; and a second layer over the first layer, the second layer containing a second material, wherein a part of the second layer extends into the first layer so as to fill a crack gap of the first layer, wherein a resistance increase rate of a resistance value of the wiring from before a bending test to after the bending test is 7.0% or less, the bending test being performed using a tension-free planar body U-shape folding test machine under a test condition where a length of the wiring is 40 mm, a bending radius is 5 mm, and a bending number is 100 times.

30 . The wiring according to claim 29 ,
wherein the second layer covers side and top surfaces of the first layer.

31 . The wiring according to claim 29 ,
wherein the first material is an alloy.

32 . The wiring according to claim 31 ,
wherein the alloy contains nickel and phosphorus.

33 . The wiring according to claim 29 ,
wherein the second material contains gold or copper.

34 . The wiring according to claim 29 ,
wherein the substrate is flexible.

35 . The wiring according to claim 29 ,
wherein the substrate contains a resin material.

36 . A wiring provided on a substrate, comprising:
a first layer and a second layer in order from bottom in the film thickness direction, wherein the first layer includes a first region containing a first material and a second region containing a second material, wherein the second layer contains the second material, wherein the second region fills a crack gap of the first region.

37 . The wiring according to claim 36 , further comprising:
a third layer under the first layer in the film thickness direction, wherein the third layer contains the first material.

38 . A transistor,
wherein at least one electrode among a gate electrode, a source electrode, and a drain electrode is formed of the wiring according to claim 29 .

39 . A transistor,
wherein at least one electrode among a gate electrode, a source electrode, and a drain electrode is formed of the wiring according to claim 36 .

40 . An electronic device comprising:
the transistor according to claim 38 .

41 . An electronic device comprising:
the transistor according to claim 39 .

42 . A method of manufacturing a wiring, comprising the steps of:
forming a first layer containing a first material over at least part on a substrate; forming a crack in the first layer; and forming a second layer containing a second material inside the first layer so as to fill the crack in the first layer and over a top of the first layer.

43 . The method of manufacturing the wiring according to claim 42 , further comprising:
etching the first layer before forming the second layer.

44 . The method of manufacturing the wiring according to claim 42 , further comprising:
after forming the second layer,
forming a resist layer over the second layer,
irradiating the resist layer with pattern light and developing,
etching the second layer and the first layer after the developing, and
removing the developed resist layer, after etching the second layer and the first layer.

45 . The method of manufacturing the wiring according to claim 42 ,
wherein the step of forming the first layer comprises:
forming a resist layer over the substrate,
irradiating the resist layer with patterned light and developing the resist layer,
forming the first layer containing the first material over the substrate exposed after developing the resist layer.

46 . The method of manufacturing the wiring according to claim 42 ,
wherein the first material contains nickel and phosphorus.

47 . The method of manufacturing the wiring according to claim 42 ,
wherein in the step of forming the first layer, the first layer containing nickel and phosphorus is formed over at least part of the substrate by electroless plating.

48 . The method of manufacturing the wiring according to claim 42 ,
wherein the second material contains gold or copper.

49 . The method of manufacturing the wiring according to claim 42 ,
wherein in the step of forming the second layer, the second layer containing gold or copper is formed by bringing a displacement gold plating bath or a displacement copper plating bath into contact with the first layer having the crack.

50 . The method of manufacturing the wiring according to claim 42 ,
wherein the substrate is flexible.

51 . The method of manufacturing the wiring according to claim 42 ,
wherein the substrate contains a resin material.

52 . The method of manufacturing the wiring according to claim 42 ,
wherein the substrate has a sheet shape.

53 . The method of manufacturing the wiring according to claim 42 ,
wherein in the step of forming the crack, the crack is formed by conveying the substrate using a dancer roller mechanism or a rolling roller mechanism.

54 . The method of manufacturing the wiring according to claim 42 ,
wherein a phosphorus content of the first layer is smaller than a nickel content of the first layer.

55 . The method of manufacturing the wiring according to claim 42 ,
wherein the wiring corresponds to a circuit pattern for an electronic device.

56 . A method of manufacturing a transistor, comprising:
forming at least one electrode among a gate electrode, a source electrode, and a drain electrode by the method of manufacturing the wiring according to claim 42 .

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Kito Yoshiaki
• Kawabata Seiji
• Kiuchi Tohru

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P14/46

  using a liquid · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title