Semiconductor element and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-2019393173-A1
Application number	US-201816481995-A
Country	US
Kind code	A1
Filing date	Feb 7, 2018
Priority date	Feb 15, 2017
Publication date	Dec 26, 2019
Grant date	—

Abstract

Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder.

First claim

1 - 14 . (canceled)

15 . A semiconductor element, comprising: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate,
wherein the electroless plating layer includes: an electroless nickel-phosphorus plating layer formed on the at least one of the electrodes; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has recesses formed on a surface thereof to be joined with solder.

16 . The semiconductor element according to claim 15 , wherein the at least one of the electrodes has a flat surface.

17 . The semiconductor element according to claim 16 , wherein the at least one of the electrodes has a surface flatness of 0.005 μm or more and 0.15 μm or less in terms of Ra value.

18 . The semiconductor element according to claim 15 , wherein the recesses formed on the surface of the electroless plating layer have a depth of 0.05 μm or more and 1.5 μm or less.

19 . The semiconductor element according to claim 16 , wherein the recesses formed on the surface of the electroless plating layer have a depth of 0.05 μm or more and 1.5 μm or less.

20 . The semiconductor element according to claim 17 , wherein the recesses formed on the surface of the electroless plating layer have a depth of 0.05 μm or more and 1.5 μm or less.

21 . The semiconductor element according to claim 15 , wherein the recesses formed on the surface of the electroless plating layer have a diameter of 0.05 μm or less.

22 . The semiconductor element according to claim 16 , wherein the recesses formed on the surface of the electroless plating layer have a diameter of 0.05 μm or less.

23 . The semiconductor element according to claim 17 , wherein the recesses formed on the surface of the electroless plating layer have a diameter of 0.05 μm or less.

24 . The semiconductor element according to claim 18 , wherein the recesses formed on the surface of the electroless plating layer have a diameter of 0.05 μm or less.

25 . The semiconductor element according to claim 15 ,
wherein the electroless nickel-phosphorus plating layer comprises two electroless nickel-phosphorus plating layers having different nickel concentrations, and wherein the electroless nickel-phosphorus plating layer on a side closer to the electroless gold plating layer has a higher nickel concentration than the electroless nickel-phosphorus plating layer on a side closer to the at least one of the electrodes.

26 . The semiconductor element according to claim 16 ,
wherein the electroless nickel-phosphorus plating layer comprises two electroless nickel-phosphorus plating layers having different nickel concentrations, and wherein the electroless nickel-phosphorus plating layer on a side closer to the electroless gold plating layer has a higher nickel concentration than the electroless nickel-phosphorus plating layer on a side closer to the at least one of the electrodes.

27 . The semiconductor element according to claim 17 ,
wherein the electroless nickel-phosphorus plating layer comprises two electroless nickel-phosphorus plating layers having different nickel concentrations, and wherein the electroless nickel-phosphorus plating layer on a side closer to the electroless gold plating layer has a higher nickel concentration than the electroless nickel-phosphorus plating layer on a side closer to the at least one of the electrodes.

28 . The semiconductor element according to claim 15 , wherein the electroless plating layer is joined with solder to at least one selected from the group consisting of an external terminal and a heat dissipation substrate.

29 . A method of manufacturing a semiconductor element, comprising the steps of:
forming a front-side electrode on a front-back conduction-type substrate; and sequentially forming an electroless nickel-phosphorus plating layer and an electroless gold plating layer on the front-side electrode, the step of forming the electroless nickel-phosphorus plating layer on the front-side electrode comprising performing electroless nickel-phosphorus plating treatment while increasing at least one selected from the group consisting of a nickel concentration, a pH, a temperature, and a stirring rate of an electroless nickel-phosphorus plating solution.

30 . A method of manufacturing a semiconductor element, comprising the steps of:
forming a front-side electrode on a front-back conduction-type substrate; and sequentially forming an electroless nickel-phosphorus plating layer and an electroless gold plating layer on the front-side electrode, the step of forming the electroless nickel-phosphorus plating layer on the front-side electrode comprising performing electroless nickel-phosphorus plating treatment while changing at least one selected from the group consisting of a rocking rate and a rocking width.

31 . The method of manufacturing a semiconductor element according to claim 29 , wherein the step of forming the electroless nickel-phosphorus plating layer is performed by a zincate method.

32 . The method of manufacturing a semiconductor element according to claim 30 , wherein the step of forming the electroless nickel-phosphorus plating layer is performed by a zincate method.

33 . The method of manufacturing a semiconductor element according to claim 29 , wherein the method further comprises a step of, after forming the front-side electrode using aluminum or an aluminum alloy, heating to melt the aluminum or the aluminum alloy, to thereby flatten surfaces of the front-side electrode.

34 . The method of manufacturing a semiconductor element according to claim 30 , wherein the method further comprises a step of, after forming the front-side electrode using aluminum or an aluminum alloy, heating to melt the aluminum or the aluminum alloy, to thereby flatten surfaces of the front-side electrode.

Assignees

• Mitsubishi Electric Corp

Inventors

• Sunamoto Masatoshi
• Ueno Ryuji

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/90

  Bond pads, in general · CPC title