Wiring pattern production method and transistor production method

Patent metadata

Field	Value
Publication number	US-2016359115-A1
Application number	US-201615243146-A
Country	US
Kind code	A1
Filing date	Aug 22, 2016
Priority date	Feb 28, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

A wiring pattern production method includes forming, on a substrate, a precursor film for a plating base film including a first formation material having an amino group protected by a photoreactive protecting group, forming a photoresist layer including a photoresist material on a surface of the precursor film, exposing the photoresist layer with a desired pattern of light, exposing the precursor film with a desired pattern of light to form the plating base film, developing the exposed photoresist layer, removing a deprotected protecting group, and depositing an electroless plating catalyst on the exposed surface of the plating base film.

First claim

What is claimed is:

1 . A wiring pattern production method comprising:
forming, on a substrate, a precursor film for a plating base film including a first formation material having an amino group protected by a photoreactive protecting group; forming a photoresist layer including a photoresist material on a surface of the precursor film; exposing the photoresist layer with a desired pattern of light; exposing the precursor film with a desired pattern of light to form the plating base film; developing the exposed photoresist layer and removing a deprotected protecting group; and depositing an electroless plating catalyst on the exposed surface of the plating base film.

2 . The wiring pattern production method according to claim 1 , wherein the exposing of the photoresist layer and the exposing of the precursor film are simultaneously performed.

3 . The wiring pattern production method according to claim 1 , wherein, after removing the photoresist layer, the exposed plating base film is further exposed.

4 . The wiring pattern production method according to claim 1 , wherein the protecting group is an o-nitrobenzyl group or a group having an o-nitrobenzyl skeleton.

5 . The wiring pattern production method according to claim 1 , wherein the amino group is a group represented by —NH 2 .

6 . The wiring pattern production method according to claim 1 , wherein the first formation material is a silane coupling agent having an amino group protected by the protecting group.

7 . The wiring pattern production method according to claim 1 , wherein the precursor film includes a group having at least one of a nitrogen atom and a sulfur atom and the group having the at least one of the nitrogen atom and the sulfur atom further includes a second formation material which is not protected by the protecting group.

8 . The wiring pattern production method according to claim 7 , wherein the second formation material is a silane coupling agent having the group having the at least one of the nitrogen atom and the sulfur atom.

9 . The wiring pattern production method according to claim 1 , wherein the substrate is made of a nonmetallic material.

10 . The wiring pattern production method according to claim 9 , wherein the substrate is made of a resin material.

11 . The wiring pattern production method according to claim 10 , wherein the substrate has flexibility.

12 . A transistor production method comprising:
forming at least one of a gate electrode, a source electrode, and a drain electrode on a substrate using the wiring pattern production method according to claim 1 .

13 . The transistor production method according to claim 12 , comprising:
forming the gate electrode on the substrate; covering the gate electrode to form a layer including an insulator layer; and forming the source electrode and the drain electrode on a surface of the layer including the insulator layer.

14 . The transistor production method according to claim 12 , comprising:
forming the source electrode and the drain electrode on the substrate; covering the source electrode and the drain electrode to form a layer including an insulator layer; and forming the gate electrode on a surface of the layer including the insulator layer.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Sugizaki Takashi
• Kawakami Yusuke

Classifications

• H01L51/055

  Electricity · mapped topic

• H01L51/0545

  Electricity · mapped topic

• C23C18/32

  Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence) · CPC title

• C23C18/2086

  with use of organic or inorganic compounds other than metals, first · CPC title

• C23C18/1605 Primary

  by masking · CPC title