Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2024147697-A1
Application number	US-202318308376-A
Country	US
Kind code	A1
Filing date	Apr 27, 2023
Priority date	Oct 31, 2022
Publication date	May 2, 2024
Grant date	—

Abstract

A semiconductor device includes a substrate, a chip region in the substrate, a scribe lane region in the substrate, first active patterns in the chip region, a first device isolation pattern on the first active patterns, second active patterns in the scribe lane region, and a second device isolation pattern on the second active patterns. The scribe lane region is adjacent to the chip region. The first device isolation pattern includes a first device isolation material, and the second device isolation pattern includes a second device isolation material. The second device isolation material is different from the first device isolation material.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a chip region in the substrate; a scribe lane region in the substrate; first active patterns in the chip region; a first device isolation pattern on the first active patterns; second active patterns in the scribe lane region; and a second device isolation pattern on the second active patterns, wherein the scribe lane region is adjacent to the chip region, wherein the first device isolation pattern includes a first device isolation material, wherein the second device isolation pattern includes a second device isolation material, and wherein the second device isolation material is different from the first device isolation material.

2 . The semiconductor device of claim 1 , wherein the first device isolation material has a first etching rate,
wherein the second device isolation material has a second etching rate, and wherein the first etching rate is different from the second etching rate.

3 . The semiconductor device of claim 2 , wherein the second etching rate is less than or equal to 0.1 times of the first etching rate.

4 . The semiconductor device of claim 1 , wherein the first device isolation material includes silicon oxide, and
wherein the second device isolation material includes silicon nitride, silicon carbon nitride, silicon boron nitride, silicon carbon boron nitride, polysilicon, doped polysilicon, and/or a mixture thereof.

5 . The semiconductor device of claim 1 , further comprising:
bit line structures in the chip region; and key structures in the scribe lane region.

6 . The semiconductor device of claim 5 , wherein the bit line structures include a first conductive structure, a first barrier pattern, a first metal pattern, and a first capping pattern which are stacked on the substrate.

7 . The semiconductor device of claim 6 , wherein the key structures include an insulation pattern, a second conductive structure, a second barrier pattern, a second metal pattern, and a second capping pattern which are stacked on the substrate.

8 . The semiconductor device of claim 5 , wherein the bit line structures are spaced apart from each other by a first width in a first direction parallel to an upper surface of the substrate and extend in a second direction that intersects the first direction.

9 . The semiconductor device of claim 8 , wherein the key structures are spaced apart from each other by a second width in the first direction parallel to the upper surface of the substrate and extend in the second direction.

10 . The semiconductor device of claim 9 , wherein the second width is greater than the first width.

11 . A semiconductor device, comprising:
a substrate that has a chip region and a scribe lane region that surrounds the chip region in a plan view, wherein the chip region includes first active patterns, a first device isolation pattern on the first active patterns, and first gate structures on respective ones of the first active patterns and on the first device isolation pattern, wherein the scribe lane region includes second active patterns and a second device isolation pattern on the second active patterns, wherein the first device isolation pattern includes a first device isolation material, wherein the second device isolation pattern includes a second device isolation material, and wherein the second device isolation material has an etch selectivity with respect to the first device isolation material.

12 . The semiconductor device of claim 11 , wherein the first gate structures each includes a first gate insulation layer on the first active patterns and the substrate, a first gate electrode on the first gate insulation layer, and a first gate mask on the first gate electrode.

13 . The semiconductor device of claim 11 , wherein the first gate structures extend in a first direction parallel to an upper surface of the substrate and are spaced apart from each other in a second direction that intersects the first direction.

14 . A semiconductor device, comprising:
a substrate that has a chip region, and a scribe lane region that surrounds the chip region in a plan view; bit line structures on the chip region; and key structures on the scribe lane region, wherein the chip region includes first active patterns, a first device isolation pattern between the first active patterns, and first gate structures on respective ones of the first active patterns and on the first device isolation pattern, wherein the scribe lane region includes second active patterns and a second device isolation pattern between the second active patterns, wherein the first device isolation pattern includes a first device isolation material, wherein the second device isolation pattern includes a second device isolation material, and wherein the second device isolation material has an etch selectivity with respect to the first device isolation material.

15 . The semiconductor device of claim 14 , wherein the bit line structures are spaced apart from each other by a first width in a first direction parallel to an upper surface of the substrate and extend in a second direction that intersects the first direction.

16 . The semiconductor device of claim 14 , wherein the key structures are spaced apart from each other by a second width in a first direction parallel to an upper surface of the substrate and extend in a second direction that intersects the first direction.

17 . The semiconductor device of claim 14 , wherein the first gate structures extend in a first direction parallel to an upper surface of the substrate and are spaced apart from each other in a second direction that intersects the first direction.

18 . The semiconductor device of claim 14 , further comprising:
a lower contact plug on a respective one of the first active patterns and the first device isolation pattern between the bit line structures; and an upper contact plug on the lower contact plug.

19 . The semiconductor device of claim 18 , further comprising:
a fill pattern on the second device isolation pattern between the key structures; and an upper contact layer on the second active patterns and the key structures.

20 . The semiconductor device of claim 19 , further comprising:
a capacitor on the upper contact plug, wherein the capacitor includes a lower electrode on the upper contact plug, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yanghee
• Kwon Byoungho
• Kim Seongeun
• Kim Sujeong
• Park Jonghyuk
• Yoon Ilyoung
• Jang Woohyuk
• Joo Byungsoo

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/482

  Bit lines · CPC title

• H10W46/503

  Located in scribe lines · CPC title