Power supply suppression circuit, chip and communication terminal

Patent metadata

Field	Value
Publication number	US-2024143005-A1
Application number	US-202418408535-A
Country	US
Kind code	A1
Filing date	Jan 9, 2024
Priority date	Aug 6, 2021
Publication date	May 2, 2024
Grant date	—

Abstract

A power supply suppression circuit ( 10 ), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit ( 10 ) comprises a sampling unit ( 105 ), a compensation unit ( 106 ), and an amplification unit ( 107 ). The sampling unit ( 105 ) is connected to the compensation unit ( 106 ), and the compensation unit ( 106 ) is connected to the amplification unit ( 107 ). The power supply suppression circuit ( 10 ) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).

First claim

1 . A power supply suppression circuit, comprising a sampling unit, a compensation unit, and an amplification unit, wherein the sampling unit is connected to the compensation unit, and the compensation unit is connected to the amplification unit; and
a first AC signal within a target frequency band is obtained from a preset sampling node position of a low dropout regulator by using the sampling unit and is outputted to the compensation unit, after the compensation unit calculates a difference between the first AC signal and a second AC signal obtained from an error amplification stage of the low dropout regulator, a third AC signal in phase or out of phase with a power supply voltage is obtained and is outputted to the amplification unit, and an enhanced signal in phase with an AC signal on a power supply is generated and outputted to an output end of the error amplification stage of the low dropout regulator.

2 . The power supply suppression circuit according to claim 1 , wherein
the preset sampling node position is any one of a node position of an output port of the low dropout regulator, a node position of the power supply voltage or a ground cable connected to the low dropout regulator, and a node position on the low dropout regulator where an AC signal of an input end of a power output stage of the low dropout regulator is directly or indirectly controlled.

3 . The power supply suppression circuit according to claim 1 , wherein
the sampling unit comprises a second resistor, a third capacitor, a third resistor, a fourth resistor, and a fifth resistor, one end of the third resistor is connected to an output port of the low dropout regulator, the other end of the third resistor is connected to one end of the third capacitor and one end of the fourth resistor, the other end of the third capacitor is connected to one end of the second resistor, the other end of the fourth resistor is grounded via the fifth resistor, and the other end of the second resistor is connected to an input end of the compensation unit.

4 . The power supply suppression circuit according to claim 1 , wherein
the sampling unit comprises a sixth resistor and a fourth capacitor, one end of the fourth capacitor is connected to a ground cable end connected to the low dropout regulator, the other end of the fourth capacitor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to an input end of the compensation unit.

5 . The power supply suppression circuit according to claim 3 , wherein
the compensation unit is implemented by using a fifth PMOS transistor, a gate end of the fifth PMOS transistor is connected to an output end of the sampling unit, a source end of the fifth PMOS transistor is connected to the power supply voltage, and a drain end of the fifth PMOS transistor is connected to an input end of the amplification unit.

6 . The power supply suppression circuit according to claim 5 , wherein
the amplification unit comprises a fourth NMOS transistor and the fifth PMOS transistor, a drain end of the fourth NMOS transistor is connected to the drain end of the fifth PMOS transistor and a gate end of a sixth PMOS transistor, a gate end of the fourth NMOS transistor is connected to a gate end and a drain end of a second NMOS transistor of the low dropout regulator, and a source end of the fourth NMOS transistor is grounded.

7 . The power supply suppression circuit according to claim 1 , wherein
the sampling unit comprises a seventh resistor and a fifth capacitor, one end of the fifth capacitor is connected to the power supply voltage connected to the low dropout regulator, the other end of the fifth capacitor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to an input end of the compensation unit.

8 . The power supply suppression circuit according to claim 7 , wherein
the compensation unit is implemented by using a third NMOS transistor, a gate end of the third NMOS transistor is connected to an output end of the sampling unit, a drain end of the third NMOS transistor is connected to an input end of the amplification unit, and a source end of the third NMOS transistor is grounded.

9 . The power supply suppression circuit according to claim 8 , wherein
the amplification unit comprises a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, and the third NMOS transistor, a drain end of the fourth PMOS transistor is connected to a gate end of the fourth PMOS transistor and the drain end of the third NMOS transistor, the gate end of the fourth PMOS transistor is connected to a gate end of the fifth PMOS transistor, a source end of the fourth PMOS transistor and a source end of the fifth PMOS transistor are connected to the power supply voltage, a drain end of the fifth PMOS transistor is connected to a drain end of the fourth NMOS transistor and a gate end of a sixth PMOS transistor, a gate end of the fourth NMOS transistor is connected to a gate end and a drain end of a second NMOS transistor of the low dropout regulator, and a source end of the fourth NMOS transistor is grounded.

10 . An integrated circuit chip, comprising the power supply suppression circuit according to claim 1 .

11 . A communication terminal, comprising the power supply suppression circuit according to claim 1 .

12 . The power supply suppression circuit according to claim 4 , wherein
the compensation unit is implemented by using a fifth PMOS transistor, a gate end of the fifth PMOS transistor is connected to an output end of the sampling unit, a source end of the fifth PMOS transistor is connected to the power supply voltage, and a drain end of the fifth PMOS transistor is connected to an input end of the amplification unit.

13 . The power supply suppression circuit according to claim 12 , wherein
the amplification unit comprises a fourth NMOS transistor and the fifth PMOS transistor, a drain end of the fourth NMOS transistor is connected to the drain end of the fifth PMOS transistor and a gate end of a sixth PMOS transistor, a gate end of the fourth NMOS transistor is connected to a gate end and a drain end of a second NMOS transistor of the low dropout regulator, and a source end of the fourth NMOS transistor is grounded.

Assignees

• Vanchip Tianjin Tech Co Ltd

Inventors

• Li Chunling
• Wang Yongshou
• Chen Cheng
• Lin Sheng

Classifications

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G01R19/2509

  Details concerning sampling, digitizing or waveform capturing · CPC title