Dual loop voltage regulator based on inverter amplifier and voltage regulating method thereof

Patent metadata

Field	Value
Publication number	US-9577613-B2
Application number	US-201514961526-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Dec 11, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

First claim

What is claimed is:

1. A voltage regulator comprising:
a pass element having a power input connected to a voltage source, a power output connected to a load, and a control input;
a buffer having an input and having an output connected to the control input of the pass element;
an error amplifier forming a first feedback loop together with the pass element and the buffer and having a positive input connected to a sampled voltage of the power output of the pass element, a negative input connected to a reference voltage, and an output connected to the input of the buffer; and
a fast push-pull driver connected between the power output and the control input of the pass element in an inverter type amplification structure and configured to reduce a negative peak and a positive peak of the power output due to a variation in the load at a speed faster than a voltage regulating speed of the first feedback loop.

2. The voltage regulator of claim 1 , wherein the fast push-pull driver forms a second feedback loop together with the pass element, an operating speed of the second feedback loop being faster than an operating speed of the first feedback loop.

3. The voltage regulator of claim 1 , wherein the fast push-pull driver comprises:
a first amplifier of an inverter type and configured to generate an inverting output in response to the power output of the pass element; and
a second amplifier of the inverter type and configured to generate a push driving current or a pull driving current for controlling a voltage level of the control input in response to the inverting output.

4. The voltage regulator of claim 3 , wherein the fast push-pull driver further comprises a high-pass filter connected to the power output of the pass element and configured to perform alternating current (AC) coupling.

5. The voltage regulator of claim 4 , wherein:
the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage, a gate connected to the power output, and a drain connected to the inverting output; and a first NMOS transistor having a drain connected to the inverting output, a gate connected to the power output, and a source connected to a ground voltage, and
the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the inverting output, and a drain connected to the control input; and a second NMOS transistor having a drain connected to the control input, a gate connected to the inverting output, and a source connected to the ground voltage.

6. The voltage regulator of claim 4 , wherein:
the first amplifier comprises a first current source connected to a power supply voltage; a first PMOS transistor having a source connected to an output of the first current source, a gate connected to the power output, and a drain connected to the inverting output; a first NMOS transistor having a drain connected to the inverting output and a gate connected to the power output; and a second current source connected between a source of the first NMOS transistor and a ground voltage, and
the second amplifier comprises a third current source connected to the power supply voltage; a second PMOS transistor having a source connected to an output of the second current source, a gate connected to the inverting output, and a drain connected to the control input; a second NMOS transistor having a drain connected to the control input and a gate connected to the inverting output; and a fourth current source connected between a source of the second NMOS transistor and the ground voltage.

7. The voltage regulator of claim 4 , wherein:
the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output; a third PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to the power output, and a drain connected to the inverting output; a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and a third NMOS transistor having a drain connected to the inverting output, a gate connected to the power output, and a source connected to a drain of the first NMOS transistor; and
the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverting output; a fourth PMOS transistor having a source connected to a drain of the second PMOS transistor, a gate connected to the inverting output, and a drain connected to the control input; a second NMOS transistor having a gate connected to the inverting output and a source connected to the ground voltage; and a fourth NMOS transistor having a drain connected to the control input, a gate connected to the inverting output, and a source connected to a drain of the second NMOS transistor.

8. The voltage regulator of claim 4 , wherein:
the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output; a third PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to a first control voltage, and a drain connected to the inverting output; a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and a third NMOS transistor having a drain connected to the inverting output, a gate connected to a second control voltage, and a source connected to a drain of the first NMOS transistor; and
the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverting output; a fourth PMOS transistor having a source connected to a drain of the second PMOS transistor, a gate connected to the first control voltage, and a drain connected to the control input; a second NMOS transistor having a gate connected to the inverting output and a source connected to the ground voltage; and a fourth NMOS transistor having a drain connected to the control input, a gate connected to the second control voltage, and a source connected to a drain of the second NMOS transistor.

9. The voltage regulator of claim 4 , wherein:
the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output; a third PMOS transistor having a source connected to a drain of the first PMOS transistor and a gate connected to the power output; a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and a third NMOS transistor having a drain connected to a drain of the third PMOS transistor, a gate connected to the power output, and a source connected to a drain of the first NMOS transistor; and
the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the drain of the first PMOS transistor, and a drain connected to the control input; and a second NMOS transistor having a gate connected to the drain of the first NMOS transistor, a drain connected to the control input, and a source connected to the ground voltage.

10. The voltage regulator of claim 1 , further comprising a frequency compensation element connected between the power output of the pass element and the input of the buffer and configured to stabilize a frequency of a whole circuit loop.

11. A voltage regulator comprising:
a pass element having a power input connected to a voltage source, a power output connected to a load, and a control input;
a buffer having an input and having an output connecte

Assignees

• Yang Junhyeok
• Kim Dae-Yong
• Yoo Sungmin
• Samsung Electronics Co Ltd

Inventors

• Yang Junhyeok
• Kim Dae-Yong
• Yoo Sungmin

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• G05F1/562

  with a threshold detection shunting the control path of the final control device · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/561

  Voltage to current converters (amplifiers H03F) · CPC title