Electronic device with fine pitch and thick conductors and method of making the same

Patent metadata

Field	Value
Publication number	US-2024128005-A1
Application number	US-202318463542-A
Country	US
Kind code	A1
Filing date	Sep 8, 2023
Priority date	Oct 14, 2022
Publication date	Apr 18, 2024
Grant date	—

Abstract

The invention provides an electronic device and its manufacturing method. The electronic device includes a first conductive component, which includes a first seed layer, a first conductive layer, a first conductive thickening layer, and a first insulating layer. The first seed layer has a plurality of first seed blocks. The first conductive layer has a plurality of first conductive blocks. Each of the first conductive blocks is disposed on a top surface of the first seed block, respectively. The first conductive thickening layer has a plurality of first conductive thickened blocks, which covers one side surface of each first seed block and one side surface of each first conductive block respectively. The first insulating layer covers the first seed layer, the first conductive layer, and the first conductive thickening layer.

First claim

What is claimed is:

1 . An electronic device, comprising:
a conductive component, comprising:
a seed layer, which has a plurality of seed blocks;
a conductive layer having a plurality of conductive blocks respectively disposed on a top surface of each seed block, wherein the top surfaces of the conductive blocks are either in a flat coplanar shape;
a conductive thickening layer disposed at a lateral surface of each seed block and a lateral surface of each conductive block, wherein the top surfaces of the conductive blocks are either not disposed with the conductive thickening layer or are all disposed with the conductive thickening layer; and
an insulating layer, which dads the seed layer, the conductive layer, and the conductive thickening layer.

2 . The electronic device of claim 1 further comprises a plurality of additional conductive components, wherein the additional conductive components are integrated in a stacked arrangement.

3 . The electronic device of claim 2 further comprises a core layer structure with a conductive circuit, wherein both a top and a bottom surfaces of the core layer are integrated with a plurality of stacked conductive components, wherein the conductive components are correspondingly and identically.

4 . The electronic device of claim 1 further comprises a core layer structure with a conductive circuit, wherein both a top and a bottom surfaces of the core layer are integrated with the single conductive component, wherein the conductive components are correspondingly and identically.

5 . The electronic device of claim 1 , wherein the material of the seed layer comprises one of copper, nickel, silver, palladium, tin, and titanium, or a combination thereof, or an alloy of a combination thereof.

6 . The electronic device of claim 1 , wherein the material of the conductive layer and/or the conductive thickening layer comprises one of copper, nickel, iron, cobalt, zinc, manganese, or a combination thereof, or an alloy of a combination thereof, wherein the conductive layer and the conductive thickening layer are made of the same or different materials.

7 . A manufacturing method of an electronic device, comprising:
proving a carrier board; forming a seed layer on a surface of the carrier board; forming a photoresist layer with a plurality of openings on the seed layer by patterning lithography process and electroplating to form a plurality of conductive blocks within the openings, wherein the conductive blocks are formed as a patterned conductive layer; removing the photoresist layer to expose part of the surface of the seed layer and to expose a lateral surface and a top surface of the conductive blocks, wherein a plurality of seed blocks are formed at the seed layer clad by the conductive blocks; removing the seed layer, which is not clad by the conductive blocks; forming a conductive thickening layer to clad the lateral surface of the seed blocks and to clad the lateral surface and the top surface of the conductive blocks; forming an insulating layer with an insulating material to clad the conductive thickening layer and the surface of the carrier board; and removing the carrier board to expose the seed blocks and a bottom surface of the insulating layer, wherein the seed layer, the conductive layer, the conductive thickening layer, and the insulating layer form a conductive component.

8 . The manufacturing method of the electronic device of claim 7 , wherein before performing the step of removing the carrier board, further comprising:
performing a leveling process to remove a part of the insulating layer, a part of the conductive thickening layer, and a part of the conductive blocks so that the top surfaces of the conductive blocks form a flat coplanar surface; and forming another insulating layer on the insulating layer with an insulating material to clad the conductive thickening layer, the top surfaces of the conductive blocks, and the surface of the insulating layer, which are exposed.

9 . The manufacturing method of the electronic device of claim 7 , wherein before performing the step of removing the photoresist layer, further comprising:
performing a leveling process to remove a part of the photoresist layer and a part of the conductive blocks so that the top surfaces of the conductive blocks form a flat coplanar surface; and no other leveling process is performed in other subsequent process.

10 . The manufacturing method of the electronic device of claim 7 , wherein before performing the step of removing the carrier board, further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components.

11 . The manufacturing method of the electronic device of claim 8 , wherein before performing the step of removing the carrier board, further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components.

12 . The manufacturing method of the electronic device of claim 9 , wherein before performing the step of removing the carrier board, further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components.

13 . The manufacturing method of the electronic device of claim 7 , further comprises synchronously executing all the processes described in claim 7 on another surface of the carrier board to simultaneously form another conductive component corresponding to the conductive component on the bottom surface of the carrier board, wherein the carrier board is a core layer structure with a conductive circuit, and the carrier board is not removed in subsequent processes.

14 . The manufacturing method of the electronic device of claim 13 , further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components on a top surface and a bottom surface of the core layer structure, respectively.

15 . The manufacturing method of the electronic device of claim 8 , further comprises synchronously executing all the processes described in claim 8 on another surface of the carrier board to simultaneously form another conductive component corresponding to the conductive component on the bottom surface of the carrier board, wherein the carrier board is a core layer structure with a conductive circuit, and the carrier board is not removed in subsequent processes.

16 . The manufacturing method of the electronic device of claim 15 , further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components on a top surface and a bottom surface of the core layer structure, respectively.

17 . The manufacturing method of the electronic device of claim 9 , further comprises synchronously executing all the processes described in claim 9 on another surface of the carrier board to simultaneously form another conductive component corresponding to the conductive component on the bottom surface of the carrier board, wherein the carrier board is a core layer structure with a conductive circuit, and the carrier board is not removed in subsequent processes.

18 . The manufacturing method of the electronic device of claim 17 , further comprises repeating the process of forming the conductive component several times to form a plurality of stacked conductive components on a top surface and a bottom surface of the core layer structure, respectively.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping

Classifications

• H05K2201/09672

  Superposed layout, i.e. in different planes · CPC title

• H05K1/0265

  characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections · CPC title

• H05K1/165

  incorporating printed inductors · CPC title

• H05K3/243

  characterised by selective plating, e.g. for finish plating of pads (selective plating for making the circuit pattern H05K3/108, H05K3/182) · CPC title

• H05K3/205

  using a pattern electroplated or electroformed on a metallic carrier · CPC title