Block by deck operations for NAND memory

Patent metadata

Field	Value
Publication number	US-10325665-B2
Application number	US-201715836124-A
Country	US
Kind code	B2
Filing date	Dec 8, 2017
Priority date	Dec 8, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

First claim

What is claimed is:

1. A controller for a NAND memory array, comprising:
circuitry to provide bias voltages to the NAND memory array to define three or more decks of memory cells; and
an output interface coupled to the circuitry and to wordlines (WLs) of the memory array, the circuitry, in a deck erase operation, to:
apply a first set of bias voltages via the output interface to active WLs of at least one selected deck of the three or more decks of memory cells, the selected deck to be erased; and
apply a second set of bias voltages via the output interface to active WLs of at least one unselected deck of the three or more decks of memory cells, the at least one unselected deck not to be erased,
wherein the first set of bias voltages is lower than the second set of bias voltages.

2. The controller of claim 1 , further comprising an input interface to the circuitry, to receive one or more instructions regarding a deck operation to perform on the memory array.

3. The controller of claim 2 , wherein the input interface is coupled to one or more processors, and is further to receive the one or more instructions from the one or more processors.

4. The controller of claim 1 , wherein the circuitry is further to apply the first set of bias voltages via the output interface to active WLs of an additional selected deck of memory cells, the additional selected deck also to be erased.

5. The controller of claim 1 , wherein to apply the second set of bias voltages to the active WLs includes to allow those WLs to float upwards to a source or bit line voltage of the NAND memory array.

6. The controller of claim 1 , wherein to define the three or more decks of memory cells further includes to apply a third set of bias voltages, via the output interface, to edge dummy WLs of the selected deck to form a graded transition region between the active WLs of the selected deck and a select gate adjacent to the selected deck.

7. The controller of claim 1 , wherein the selected deck is adjacent to one or more unselected decks, and wherein to define the three or more decks of memory cells further includes to apply a fourth set of bias voltages, via the output interface, to interface dummy WLs between the active WLs of the selected deck and active WLs of the unselected decks, so as to form a graded transition region between the active WLs of the selected deck and the active WLs of the unselected decks.

8. The controller of claim 1 , wherein to define the three or more decks of memory cells further includes to apply the second set of bias voltages, via the output interface, to interface dummy WLs between any two unselected decks of memory cells.

9. The controller of claim 1 , wherein the circuitry is further, in a deck erase verify operation, to:
apply a set of erase verify voltages, through the output interface, to a selected deck; and
apply a high voltage bias to each WL of each unselected deck, where the high voltage bias is higher than the erase verify voltages.

10. The controller of claim 1 , wherein the first set of bias voltages is between 0V and 0.5V.

11. The controller of claim 5 , wherein the second set of bias voltages begins to float when it is greater than or equal to the voltage on a WL switch of the memory array.

12. The controller of claim 10 , wherein the first set of bias voltages is not allowed to float during the deck erase operation.

13. A controller for a NAND memory array, comprising:
circuitry to provide bias voltages to a NAND memory array to define three or more decks of memory cells; and
an output interface coupled to the circuitry and to wordlines (WLs) of the memory array, the circuitry to,
in a deck program operation:
apply a first set of bias voltages to active WLs of a selected deck of memory cells including a WL to be programmed; and
apply a second set of bias voltages to active WLs of unselected decks of memory cells not to be programmed,
wherein the first set of bias voltages is greater than the second set of bias voltages.

14. The controller of claim 13 , further comprising an input interface to the circuitry, coupled to one or more processors, to receive one or more instructions from the one or more processors, including a deck operation to perform on the memory array.

15. The controller of claim 13 , wherein the circuitry is further to apply the first set of bias voltages, via the output interface, to active WLs of an additional selected deck of memory cells including a WL to be programmed.

16. The controller of claim 13 , wherein the first set of bias voltages comprises:
a programming voltage Vpgm, applied to the WL of the selected deck to be programmed;
and another voltage, Vpass_sel, applied to active WLs of the selected deck when they are not being programmed, where Vpgm>Vpass_sel.

17. The controller of claim 16 , wherein the circuitry is further to first lower the bias voltages on the WLs of the selected deck, and afterwards lower the bias voltages on the unselected decks.

18. A NAND memory array, comprising:
a plurality of memory cells, respectively coupled to a plurality of wordlines (WLs); and
a controller, comprising:
circuitry to provide bias voltages to the memory cells to define three or more decks of memory cells; and
an output interface coupled to the circuitry and to wordlines (WLs) of the memory array, the circuitry to,
in a deck program verify operation:
apply a first set of bias voltages to WLs of a selected deck of memory cells;
determine if one or more unselected decks of memory cells are programmed or erased; and:
in response to a determination that an unselected deck of memory cells is erased, apply a first voltage Vpassr_low 1 to WLs of the unselected deck;
or
in response to a determination that an unselected deck of memory cells is programmed, apply a second voltage Vpassr to WLs of the unselected deck,
wherein Vpassr_low 1 <Vpassr.

19. The NAND memory array of claim 18 , wherein Vpassr_low 1 is 2-3 Volts lower than Vpassr.

20. The NAND memory array of claim 18 , wherein the selected deck is one of a middle or an internal deck, and an output circuitry, following the program verify operation, is further to lower the WLs of the middle or internal deck, and hold the WLs of the non-selected decks high, to keep an electron discharge path open through a pillar of the memory array.

21. The NAND memory array of claim 20 , the output circuitry further to; first lower the WLs of the selected deck, and afterwards lower the voltage of the WLs of the unselected decks.

22. The NAND memory array of claim 18 , wherein the first set of bias voltages comprises:
a voltage Vread applied to a selected WL to be read;
a voltage Vpassr 1 applied to WLs adjacent to the selected WL; and
a voltage Vpassr applied to other programmed WLs of the selected deck.

23. A method of providing bias voltages for a deck programming operation to a NAND memory array that define three or more decks of memory cells in a deck program operation, comprising:
applying a first set of bias voltages to active WLs of a first deck of memory cells including a first WL to be programmed;
applying a second set of bias voltages to active WLs of one or more other decks of memory cells not to be programmed, wherein the first set of bias voltages is greater than the second set of bias voltages;
first lowering the bias voltages on the WLs of the first deck; and
afterwards lowering the bias voltages on the one or more other decks.

Assignees

• Intel Corp

Inventors

• Fastow Richard
• Sun Xin
• Chandrasekhar Uday
• Parat Krishna K
• Jaramillo Camila
• Sule Purval S
• Madraswala Aliasgar S

Classifications

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/3436

  Arrangements for verifying correct programming or erasure · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title