Method of making a three-dimensional memory device using dual water vapor flow oxidation and apparatus for performing the same

Patent metadata

Field	Value
Publication number	US-2024121961-A1
Application number	US-202318348727-A
Country	US
Kind code	A1
Filing date	Jul 7, 2023
Priority date	Oct 6, 2022
Publication date	Apr 11, 2024
Grant date	—

Abstract

A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

First claim

What is claimed is:

1 . A method, comprising:
forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction; and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

2 . The method of claim 1 , wherein:
the reactant gas comprises an oxidant gas; the forming the first portion of the layer comprises forming a first portion of a semiconductor oxide layer by oxidizing a portion of a first semiconductor layer located over the substrate using the oxidant gas flowing past the substrate in the first direction; and the forming the second portion of the layer comprises forming a second portion of the semiconductor oxide layer using the oxidant gas flowing past the substrate in the second direction.

3 . The method of claim 2 , wherein:
the first semiconductor layer comprises a silicon layer; the semiconductor oxide layer comprises a silicon oxide layer; and the second direction is opposite to the first direction.

4 . The method of claim 2 , further comprising:
forming a source-level sacrificial layer over the first semiconductor layer which comprises a lower source-level semiconductor layer; forming an upper source-level semiconductor layer over the source-level sacrificial layer; forming a first-tier alternating stack of first insulating layers and first sacrificial material layers over the upper source-level semiconductor layer; forming first-tier memory openings through the first-tier alternating stack, the upper source-level semiconductor layer, the source-level sacrificial layer and at least part of the lower source-level semiconductor layer; forming sacrificial first-tier opening fill portions in the first-tier memory openings; forming a second-tier alternating stack of second insulating layers and second sacrificial material layers over the first-tier alternating stack; forming second-tier memory openings through the second-tier alternating stack to expose the sacrificial first-tier opening fill portions; removing the sacrificial first-tier opening fill portions through the second-tier memory openings to form inter-tier memory openings, wherein each inter-tier memory opening comprises a combination of a respective one of the first tier-memory openings and a respective one of the second-tier memory openings; forming memory stack structures in the inter-tier memory openings, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film; forming a backside trench vertically extending through the alternating stack, the upper source-level semiconductor layer, and at least part of the source-level sacrificial layer; removing the source-level sacrificial layer through the backside trench to form a source cavity; exposing sidewalls of the vertical semiconductor channels in the source cavity; forming a source contact layer in the source cavity through the backside trench, wherein the source contact layer contacts the sidewalls of the vertical semiconductor channels exposed in the source cavity; and replacing the sacrificial material layers with electrically conductive layers through the backside trench.

5 . The method of claim 4 , wherein forming the semiconductor oxide layer comprises forming a first sacrificial semiconductor oxide portion on a portion of the lower source-level semiconductor layer exposed in each of the first-tier memory openings.

6 . The method of claim 5 , wherein the sacrificial semiconductor oxide portion protects the lower source-level semiconductor layer during the step of removing the sacrificial first-tier opening fill portions.

7 . The method of claim 6 , further comprising forming a second sacrificial semiconductor oxide portion on a portion of the upper source-level semiconductor layer exposed in each of the first-tier memory openings simultaneously with the step of forming the first sacrificial semiconductor oxide portion on the portion of the lower source-level semiconductor layer exposed in each of the first-tier memory openings.

8 . The method of claim 7 , further comprising selectively removing the first and the second sacrificial semiconductor oxide portions after the step of removing the sacrificial first-tier opening fill portions and before the step of forming the memory stack structures.

9 . The method of claim 2 , wherein the oxidant gas comprises water vapor.

10 . The method of claim 1 , wherein:
the reactant gas comprises ammonia; the forming the first portion of the layer comprises forming a first portion of a semiconductor nitride layer by nitriding a portion of a first semiconductor layer located over the substrate using the ammonia flowing past the substrate in the first direction; and the forming the second portion of the layer comprises forming a second portion of the semiconductor nitride layer using the ammonia flowing past the substrate in the second direction.

11 . The method of claim 1 , wherein:
the reactant gas comprises a chemical vapor deposition (CVD) source gas; the forming the first portion of the layer comprises depositing the first portion of the layer by CVD using the source gas flowing past the substrate in the first direction; and the forming the second portion of the layer comprises depositing the second portion of the layer by CVD using the source gas flowing past the substrate in the second direction.

12 . The method of claim 1 , further comprising:
providing a stack of substrates comprising the substrate and a plurality of additional substrates into a vacuum chamber; forming the first portion of the layer over the stack of substrates by flowing the reactant gas past the stack of substrates in the first direction; and forming the second portion of the layer on the first portion of the layer by flowing the reactant gas past the stack of substrates in the second direction.

13 . An apparatus, comprising:
a vacuum chamber extending in a first direction and having a first orifice located at a first end of the vacuum chamber and a second orifice located proximate to a second end of the vacuum chamber; a wafer boat extending along the first direction in the vacuum chamber and configured to hold wafers thereupon; a gas distribution conduit having a first gas outlet and a second gas outlet that are fluidly connected in parallel; a first gas flow switch connected to the first gas outlet and a first connection port fluidly connected to the first orifice; a second gas flow switch connected to the second gas outlet and a second connection port fluidly connected to the second orifice; and a process controller configured to control the first gas flow switch and the second gas flow switch to provide:
a first gas flow configuration in which the reactant gas flows from the first gas outlet, through the first gas flow switch and the first connection port, and toward the first orifice; and
a second gas flow configuration in which the reactant gas flows from the second gas outlet, through the second gas flow switch and the second connection port, and toward the second orifice.

14 . The apparatus of claim 13 , wherein the reactant gas flows downwards past the wafer boat in the first gas flow configuration and the reactant gas flows upwards past the wafer boat in the second gas flow configuration.

15 . The apparatus of claim 13 , further comprising a vacuum pump fluidly connected to a vacuum conduit and having a first vacuum inlet port and a second vacuum inlet port, wherein the fir

Assignees

• Sandisk Technologies Llc

Inventors

• Hashimoto Hiraku
• Takii Eisuke
• Koyama Shin

Classifications

• H10P72/12 Primary

  Vertical boat type carrier whereby the substrates are horizontally supported, e.g. comprising rod-shaped elements · CPC title

• C23C16/4583

  the substrate being supported substantially horizontally · CPC title

• C23C16/45502

  Flow conditions in reaction chamber · CPC title

• F27B17/0025

  specially adapted for treating semiconductor wafers · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title