Circuit arrangement comprising a mos sensor, in particular tmos sensor, and a corresponding method for operating the circuit arrangement

Patent metadata

Field	Value
Publication number	US-2024106451-A1
Application number	US-202318370052-A
Country	US
Kind code	A1
Filing date	Sep 19, 2023
Priority date	Sep 20, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.

First claim

1 . A circuit arrangement, comprising:
a first integrated circuit die comprising:
a sensor circuit comprising a first FET and a second FET arranged in a differential pair and configured to supply a differential current at a respective first node and a respective second node; and
a circuit configured to switch a sign of said differential current according to a period of complementary phase clock signals;
a second integrated circuit die comprising:
an electronic reading circuit comprising a differential current reading circuit including a first input terminal coupled to said second node and a second input terminal coupled to said first node, said differential current reading circuit comprising a current to voltage converter coupled to the first and second input terminals and an analog to digital converter coupled to outputs of the current to voltage converter and configured to output a digital signal; and
a circuit configured to operate a selection of signals at its output depending on a value of said period of the complementary phase clock signals, select said differential current and eliminate spurious currents;
an ESD protection circuit interposed between at least said first and second node of said sensor circuit and the first and second input terminals of said differential current reading circuit, wherein said ESD protection circuit comprises diodes applying injection of currents from voltage supply and ground at the first and second nodes of the sensor circuit and at the first and second input terminals of the differential current reading circuit and adds said spurious currents to said differential current supplied by the sensor circuit; and a phase clock signal generator generating the complementary phase clock signals, wherein the period corresponds to one of a sampling interval of said analog to digital converter or a multiple of said sampling interval.

2 . The circuit arrangement according to claim 1 , wherein said circuit configured to operate the selection of signals depending on the value of said period of the complementary phase clock signals comprises:
a chopper circuit coupled to the ESD protection circuit and configured to switch signal polarity; and a digital averaging circuit coupled to receive the digital signal from the analog to digital converter and perform an averaging over a window of sampling intervals which is double of said period of the complementary phase clock signals.

3 . The circuit arrangement according to claim 2 , wherein said chopper circuit i s coupled to the input of the analog to digital converter.

4 . The circuit arrangement according to claim 2 , wherein said chopper circuit i s coupled to the output of the analog to digital converter and operates digitally.

5 . The circuit arrangement according to claim 1 , wherein said circuit configured to operate the selection of signals depending on the value of said period of the complementary phase clock signals comprises a bandpass sigma delta converter and further comprising a digital averaging circuit coupled to an output of the bandpass sigma delta analog to digital converter and configured to operate as a decimation filter with respect to the output of the bandpass sigma delta converter.

6 . The circuit arrangement according to claim 1 , wherein:
said circuit configured to switch the sign of said differential sensor current according to said period of the complementary phase clock signals comprises a further first differential pair and second differential pair of FETs coupled between the first FETs and the first node and the second FETs and the second node; and wherein said phase clock signal generator generating complementary phase clock signal applies the complementary phase clock signals to drive the further first differential pair and second differential pair.

7 . The circuit arrangement according to claim 1 , wherein said sensor circuit comprises:
a first node, a second node, and a third node, where a drain terminal of said first FET i s coupled to said first node, a drain terminal of said second FET is coupled to said second node, and source terminals of said first FET and said second FET are coupled to said third node; a first bias-current generator configured to generate a bias current coupled to said first node; and a second bias-current generator configured to generate a bias current coupled to said second node; and wherein the circuit arrangement further comprises a third FET having a drain terminal coupled to said third node and a source terminal coupled to a reference voltage.

8 . The circuit arrangement according to claim 7 , wherein the second integrated circuit die further comprises a regulation circuit configured to drive a gate terminal of said third FET to regulate a common mode of a voltage at said first node and regulate a common mode of a voltage at said second node; wherein said regulation circuit is configured to drive said gate terminal of said third FET such that: (V O1 +V O1 )/2=V CM , where V O1 is the voltage at said first node, V O2 is the voltage at said second node, and V CM is the common mode.

9 . The circuit arrangement according to claim 1 , wherein said first FET and said second FET are MOS transistors.

10 . The circuit arrangement according to claim 1 , wherein said first FET and said second FET are n-channel MOS transistors.

11 . The circuit arrangement according to claim 1 , wherein said first FET and said second FET are TMOS transistors.

12 . The circuit arrangement according to claim 1 , wherein the first integrated circuit die is supported by a silicon on insulator (SOI) substrate and wherein the second integrated circuit die is supported by a bulk semiconductor substrate

13 . A method for operating a circuit arrangement according to claim 1 , comprising:
generating complementary phase clock signals having a period corresponding to the sampling interval of the analog to digital converter; and switching the sign of said differential sensor current according to said period of the complementary phase clock signals before inputting the ESD protection circuit; and operating a selection of signals at the output of the ESD protection circuit depending on the value of said period of the phase clock signals, selecting said differential sensor current and eliminating said spurious currents.

Assignees

• St Microelectronics Srl

Inventors

• Ippolito Calogero Marco
• Vaiana Michele

Classifications

• G01J5/22

  Electrical features thereof · CPC title

• G01J5/20

  using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices · CPC title

• H03M1/1255 Primary

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title