Non-integer oversampled timing recovery for higher order quadrature modulation communication systems using quadrature-phase samples

Patent metadata

Field	Value
Publication number	US-2016119114-A1
Application number	US-201414525455-A
Country	US
Kind code	A1
Filing date	Oct 28, 2014
Priority date	Oct 28, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Apparatus and method for performing entirely digital timing recovery for high bandwidth radio frequency communications. The received digital data source can be sampled from any (minimum 2×) non-integer oversampled transmitted data. This method re-samples the data through interpolation and phase adjustment. The output phase error adjusts the receiver's Analog-to-digital Convertor sampling clock to improve synchronization with the transmitter's Digital-to-analog Convertor clock phase, thus improving transmitted symbol recovery.

First claim

What is claimed is:

1 . (canceled)

2 . (canceled)

3 . (canceled)

4 . (canceled)

5 . An apparatus for timing recovery in digital communications, comprising:
a timing recovery subsystem into which quadrature-phase components of a digitized communications signal are input and a phase adjustment signal is output; and an interpolation subsystem into which said phase adjustment signal and said quadrature-phase components are input and recovered in-phase and quadrature-phase symbols are output;
wherein said timing recovery subsystem further comprises:
a buffer into which said quadrature-phase components of said digitized communications signal are input;
a gain block outputting an update gain signal;
timing recovery logic, output of which is a phase offset signal, and into which is input:
an array of buffered quadrature-phase components;
said update gain signal; and
a feedback sample of said phase offset signal; and
a lowpass filter for removing phase variability extremes in said phase offset signal; and

wherein said timing recovery logic further comprises:
a signum function calculator into which said array of buffered quadrature-phase components is input;
a first sampler into which an output of said signum function calculator is input;
an index calculator having as an input a previous iteration phase offset signal and having as an output sampling indices being input into said sampler;
a phase error calculator having as an input a real-valued array output from said sampler and having as an output an amount of and direction of current iteration phase offset within a particular sampling iteration; and
a phase adjustment block having as inputs said update gain signal, said current iteration phase offset, and said previous iteration phase offset signal and having as an output an adjusted phase offset signal; and

wherein said buffer samples said quadrature-phase components a minimum of N samples, wherein
N=┌F samp /F sym ┐; where

F sym is the symbol rate; and F samp is the sample rate; and
wherein said index calculator computes said sampling indices according to:

t
c

=

1
+

k
·
N

+

N
2

+

φ
0

t
s

=

t
c

-

N
2

t
e

=

t
c

+

N
2

wherein
t s is the start of the incoming symbol within said array;
t c is the center of the incoming symbol within said array;
t e is the end of the incoming symbol within said array;
k is a counter of which symbol is being sampled within said buffer; and
φ 0 is the previous symbol phase offset.

6 . The apparatus of claim 5 , wherein said real-valued array further comprises start (x s ), center (x c ) and end (x e ) symbols defined as:
x s =x I ( t s ) x c =x I ( t c ) x e =x I ( t e )

7 . The apparatus of claim 6 , wherein said current phase offset Δ φ is defined as:
Δ φ =( x e −x s )·( x c −Δ x )

where

Δ
x

=

x
e

-

x
s

2

8 . The apparatus of claim 3 , wherein said adjusted phase offset signal is defined as:

adjusted



phase



offset

=

{

previous



phase



offset

+

update



gain

,

if



current



phase



offset

<

-
T

previous



phas

Assignees

• Us Government

Inventors

• Wohlrab Gerard

Classifications

• H04L1/205

  jitter monitoring · CPC title

• H04L7/0029 Primary

  interpolation of received data signal · CPC title

• H03M1/1255

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H04L27/3455

  in order to facilitate carrier recovery at the receiver end, e.g. by transmitting a pilot or by using additional signal points to allow the detection of rotations · CPC title