Methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-2024081075-A1
Application number	US-202318131924-A
Country	US
Kind code	A1
Filing date	Apr 7, 2023
Priority date	Sep 2, 2022
Publication date	Mar 7, 2024
Grant date	—

Abstract

A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements; forming a plate layer on the peripheral circuit structure; forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction, perpendicular to an upper surface of the plate layer; patterning the preliminary stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers; forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers; forming selective deposition layers on exposed surfaces of the patterned sacrificial layers; forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer; forming isolation openings penetrating through the preliminary stack structure in the first direction, and extending in a second direction, parallel to an upper surface of the substrate; forming horizontal openings by removing the sacrificial layers and the selective deposition layers exposed through the isolation openings; forming gate electrodes filling the horizontal openings; and forming gate contacts electrically connected to the gate electrodes.

2 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein forming the deposition inhibition layers includes supplying an inhibitor.

3 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein forming the selective deposition layers includes supplying a precursor.

4 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein:
the interlayer insulating layers include silicon oxide or silicon nitride, and the sacrificial layers include a material different from that of the interlayer insulating layer, the material including silicon, silicon oxide, silicon carbide, or silicon nitride.

5 . The method of manufacturing a semiconductor device as claimed in claim 2 , wherein the inhibitor includes nitrogen trifluoride (NF 3 ).

6 . The method of manufacturing a semiconductor device as claimed in claim 3 , wherein the precursor includes one selected from the group consisting of hexachlorodisilane (HCD), dichlorosilane (DCS), tetrachlorosilane (TCS: SiCl 4 ), and trichlorosilane (TCS: SiCl 3 H).

7 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the deposition inhibition layer is a single layer containing a fluorine element.

8 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the forming of the selective deposition layers is performed through an atomic layer diffusion (ALD) method.

9 . The method of manufacturing a semiconductor device as claimed in claim 8 , wherein the forming of the selective deposition layers further includes an annealing operation.

10 . The method of manufacturing a semiconductor device as claimed in claim 8 , wherein the forming of the selective deposition layers further includes performing a plasma nitridation process.

11 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the gate electrodes include a pad region in which a lower gate electrode extends further in the second direction than an upper gate electrode and wherein the pad region is exposed from the interlayer insulating layers, the gate electrodes having an increased thickness in the pad region.

12 . The method of manufacturing a semiconductor device as claimed in claim 11 , wherein the gate electrodes have a curved side surface protruding from the pad region.

13 . The method of manufacturing a semiconductor device as claimed in claim 11 , wherein the gate electrodes include a first gate electrode forming the pad region and a second gate electrode lower than the first gate electrode in the first direction.

14 . The method of manufacturing a semiconductor device as claimed in claim 13 , wherein the second gate electrode has an upper surface having a protruding curved shape.

15 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the selective deposition layers include the same material as the sacrificial layers.

16 . The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the gate contacts recess upper portions of the gate electrodes.

17 . A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a plate layer in a first direction, perpendicular to an upper surface of the plate layer; patterning the preliminary stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers; forming deposition inhibition layers on exposed surfaces of the patterned aver insulating layers by supplying; an inhibitor; forming selective deposition layers on exposed surfaces of the patterned sacrificial layers by supplying a precursor; forming isolation openings penetrating through the preliminary stack structure in the first direction, and extending in a second direction, parallel to an upper surface of the plate layer; forming horizontal openings by removing the sacrificial layers and the selective deposition layers exposed through the isolation openings; and forming gate electrodes filling the horizontal openings.

18 . The method of manufacturing a semiconductor device as claimed in claim 17 , further including:
forming openings penetrating through the selective deposition layers and the preliminary stack structure in the first direction, and penetrating through the plate layer and extending further downwardly than the plate layer in the first direction, wherein the forming openings is performed after the forming of the selective deposition layers; and forming gate contacts filling at least a portion of the openings and contacting the gate electrodes, wherein the forming gate contacts is performed after the forming of the gate electrodes.

19 . The method of manufacturing a semiconductor device as claimed in claim 17 , further including:
forming a first semiconductor structure including:
a substrate,
circuit elements on the substrate, and
interconnections on the circuit elements;
forming a second semiconductor structure including:
forming the preliminary stack structure,
forming the patterned sacrificial layers and the patterned interlayer insulating layers,
forming the deposition inhibition layers,
forming the selective deposition layers,
forming the isolation openings,
forming the horizontal openings, and
forming the gate electrodes; and
bonding the first semiconductor structure and the second semiconductor structure.

20 . A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a plate layer in a first direction, perpendicular to an upper surface of the plate layer; patterning the preliminary stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers, and forming preliminary pads, regions in which the sacrificial layers are exposed u

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Byongju
• Choi Dongsung
• Park Wonjun
• Lee Donghwa
• Jung Jaemin
• Cheon Changheon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title