Method for manufacturing semiconductor device

US2024055254A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024055254-A1
Application numberUS-202117630674-A
CountryUS
Kind codeA1
Filing dateNov 12, 2021
Priority dateOct 21, 2021
Publication dateFeb 15, 2024
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

First claim

Opening claim text (preview).

1 . A method for manufacturing a semiconductor device, wherein: the semiconductor device comprises a substrate and a to-be-connected structure disposed on a side of the substrate; and the method comprises: forming a photolithographic coating on the to-be-connected structure, wherein the photolithographic coating comprises a first film, a photolithographic film, and a second film which are stacked in the above-listed sequence, and refractive indexes of the first film and the second film are smaller than 1; exposing the photolithographic coating to a light having a target wavelength through a mask, to image both the to-be-connected structure and a pattern of the mask to a target region of the photolithographic film; forming an electrical connection in contact with the to-be-connected structure at the target region. 2 . The method according to claim 1 , wherein before forming the photolithographic coating on the to-be-connected structure, the method further comprises: determining a thickness of the photolithographic coating based on: simulated light intensity, which is in the photolithographic film due to the to-be-connected structure is imaged to the photolithographic film by the light having the target wavelength, and simulated light intensity, which is in the photolithographic film due to the pattern of the mask is imaged to the photolithographic film by the light having the target wavelength. 3 . The method according to claim 1 , wherein: before forming the photolithographic coating on the to-be-connected structure, the method further comprises: forming a dielectric layer on the to-be-connected structure, wherein the dielectric layer is disposed between the to-be-connected structure and the photolithographic coating; and after exposing the photolithographic coating to the light having the target wavelength through the mask, the method further comprises: etching the dielectric layer corresponding to the target region through the photolithographic film, to obtain a contact hole running through the dielectric layer, wherein the to-be-connected structure is exposed by the contact hole. 4 . The method according to claim 3 , wherein before etching the dielectric layer corresponding to the target region through the photolithographic film, the method further comprises: removing the second film. 5 . The method according to claim 3 , wherein after etching the dielectric layer corresponding to the target region through the photolithographic film to obtain the contact hole running through the dielectric layer, the method further comprises: filling the contact hole with metal to form a metal contact, wherein the metal contact is connected with the to-be-connected structure. 6 . The method according to claim 1 , wherein the photolithographic film is made of a photoresist, and the first film and the second film are made of metal materials. 7 . The method according to claim 1 , wherein the light having the target wavelength is a red light or an ultraviolet light. 8 . The method according to claim 1 , wherein the to-be-connected structure is at least one of: a gate structure, a source structure, or a drain structure. 9 . The method according to claim 1 , wherein a feature size of the pattern of the mask ranges from 100% to 160% of a designed feature size. 10 . The method according to claim 1 , wherein a positional offset of a center of the pattern of the mask ranges from −20% to 20% of a pattern pitch.

Assignees

Inventors

Classifications

  • H10P50/73Primary

    using masks for insulating materials · CPC title

  • by forming self-aligned vias or self-aligned contact plugs · CPC title

  • by forming self-aligned vias · CPC title

  • Photolithographic processes · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2024055254A1 cover?
A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coat…
Who is the assignee on this patent?
Inst Of Microelectronics Cas
What technology area does this patent fall under?
Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 15 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).