Fan-out package structures with cascaded openings in enhancement layer

Patent metadata

Field	Value
Publication number	US-2024038701-A1
Application number	US-202217814836-A
Country	US
Kind code	A1
Filing date	Jul 26, 2022
Priority date	Jul 26, 2022
Publication date	Feb 1, 2024
Grant date	—

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

First claim

1 . A semiconductor package structure, comprising:
a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure, the enhancement layer comprising a plurality of cascaded openings, wherein each one of the cascaded openings comprises:
a primary opening defined by a first side wall and a bottom wall; and
a secondary opening extended from the bottom wall of the primary opening to the first RDL structure, wherein the secondary opening is smaller in critical dimension than the corresponding primary opening,
a plurality of pre-solder bumps electrically connected to the first RDL structure, each pre-solder bump disposed in one of the cascaded openings and horizontally aligned with the secondary opening thereof; and a plurality of solder balls disposed on and electrically connected to the second RDL structure.

2 . The semiconductor package structure of claim 1 , wherein the primary opening has a critical dimension of opening and a critical dimension of bottom, the secondary opening has a critical dimension of opening and a critical dimension of bottom, and wherein the critical dimension of opening of the secondary opening is smaller than the critical dimension of bottom of the primary opening.

3 . The semiconductor package structure of claim 1 , wherein the first side wall has a first angle of 120° or more relative to the bottom wall.

4 . The semiconductor package structure of claim 1 , wherein the secondary opening is defined by a second side wall that has a second angle of 120° or more relative to the first RDL structure.

5 . The semiconductor package structure of claim 1 , wherein the primary opening has a first depth measured from an outer surface of the enhancement layer to the bottom wall, wherein the first depth is less than a thickness of the enhancement layer.

6 . The semiconductor package structure of claim 5 , wherein the secondary opening has a second depth measured from the bottom wall to the first RDL structure, and a ratio of the first depth to the second depth is at least 4.

7 . The semiconductor package structure of claim 1 , wherein the cascaded openings are formed by laser drilling, etching, photolithography, or combinations thereof.

8 . The semiconductor package structure of claim 1 , wherein the enhancement layer has a thickness in a range from 10 μm to 100 μm.

9 . The semiconductor package structure of claim 1 , wherein the enhancement layer further comprises a laser marking region surrounded by the plurality of pre-solder bumps.

10 . The semiconductor package structure of claim 9 , wherein the laser marking region comprises a three-dimensional (3D) pattern having a plurality of recesses.

11 . The semiconductor package structure of claim 10 , wherein the plurality of
recesses have an average recess depth 50% or less relative to a thickness of the enhancement layer.

12 . The semiconductor package structure of claim 10 , wherein the 3D pattern carries identification information.

13 . The semiconductor package structure of claim 1 , further comprising an integrated passive device disposed on and electrically connected to the second RDL structure.

14 . A semiconductor package structure, comprising:
a first die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the first die; a second RDL structure disposed on and electrically connected to the frontside of the first die; a through integrated fan-out via (TIV) disposed lateral to the first die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure, the enhancement layer comprising a plurality of cascaded openings, wherein each one of the cascaded openings comprises:
a primary opening defined by a first side wall and a bottom wall; and
a secondary opening extended from the bottom wall of the primary opening to the first RDL structure, wherein the secondary opening is smaller in critical dimension than the corresponding primary opening,
a plurality of pre-solder bumps electrically connected to the first RDL structure, each pre-solder bump disposed in one of the cascaded openings and horizontally aligned with the secondary opening thereof; a printed circuit board (PCB) electrically connected to the first die through a first plurality of solder balls disposed between the second RDL structure and the PCB; and a second die electrically connected to the first RDL structure through a second plurality of solder balls, each of the second plurality of solder balls disposed in one of the cascaded openings and electrically connected to the corresponding pre-solder bump therein.

15 . The semiconductor package structure of claim 14 , further comprising an underfill disposed between the second die and the enhancement layer and between the PCB and the first RDL structure.

16 . The semiconductor package structure of claim 14 , wherein the enhancement layer further comprises a three-dimensional (3D) pattern configured to facilitate flow of an underfill between the second die and the enhancement layer.

17 . The semiconductor package structure of claim 14 , wherein the second die is dynamic random access memory (DRAM).

18 . A method of fabricating a semiconductor package structure, the method comprising:
providing a carrier; forming a first redistribution layer (RDL) structure on the carrier; forming a through integrated fan-out via (TIV), the TIV disposed on and electrically connected to the first RDL structure; disposing a first die onto the first RDL structure, the first die having a frontside and a backside, wherein the backside is in contact with the first RDL structure; disposing a molding compound over the first RDL structure to encapsulate the first die and the TIV; performing grinding to expose a portion of the TIV and a contact pad on the frontside of the first die; forming a second RDL structure over the frontside of the first die, the molding compound, and the TIV, the second RDL structure electrically connected to the contact pad of the first die; forming a first plurality of solder balls and an integrated passive device (IPD) on the second RDL structure; de-bonding the carrier from the first RDL structure to expose a surface of the first RDL structure; forming an enhancement layer on the exposed surface of the first RDL structure; forming a cascaded opening through the enhancement layer; forming and disposing a pre-solder bump into the cascaded opening, the pre-solder bump electrically connected to the first RDL structure; and forming a three-dimensional (3D) pattern on the enhancement layer.

19 . The method of claim 18 , wherein forming the cascaded opening further comprises:
forming a primary opening, the primary opening defined by a first side wall and a bottom wall; and forming a secondary opening, the secondary opening extended from the bottom wall of the primary opening to the first RDL structure, wherein the secondary opening is smaller in critical dimension than the correspondi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Ting-Ting
• Huang Li-Hsien
• Yang Tien-Chung
• Chuang Yao-Chun
• Lu Yinlung
• He Jun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title