Power device integration on a common substrate

Patent metadata

Field	Value
Publication number	US-2023420497-A1
Application number	US-202318464938-A
Country	US
Kind code	A1
Filing date	Sep 11, 2023
Priority date	Jul 31, 2012
Publication date	Dec 28, 2023
Grant date	—

Abstract

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure comprising at least one PN diode power device, the method comprising:
forming an active region; forming a buried well in the active region, the buried well having a first conductivity type; forming an anode region, having the first conductivity type, in the active region through an upper surface of the active region, the anode region being electrically connected to the buried well; forming a cathode region, having a second conductivity type, in the active region through the upper surface of the active region and disposed laterally from the anode region; forming a cathode terminal electrically connected to the cathode region; and forming an anode terminal electrically connected to the anode region; wherein: the buried well is configured, in conjunction with the cathode region, to form a clamping diode operative to position a breakdown avalanche region between the buried well and the cathode terminal, a breakdown voltage of the at least one PN diode power device being a function of one or more characteristics of the buried well; the buried well is formed proximate a lower surface of the active region and extends from the anode region to a location proximate the cathode region; and the anode region is formed on at least a portion of the buried well and extends along the upper surface of the active region 1) to the anode terminal to make electrical contact to the anode terminal and 2) to the cathode region to form a PN junction of the at least one PN diode power device with the cathode region.

2 . The method of claim 1 , further comprising:
forming a gate structure above the active region proximate the upper surface of the active region, at least partially between the cathode region and the anode region, and electrically connected to the anode terminal; wherein: the gate structure overlaps the PN junction; and the gate structure is configured to control an electric field distribution proximate the PN junction.

3 . The method of claim 2 , further comprising:
forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal.

4 . The method of claim 2 , further comprising:
forming an anode trench in the active region, wherein the anode terminal is formed at least in part in the anode trench, the anode terminal is electrically connected to the buried well and the anode region in the anode trench by a conductive layer, and the anode terminal is electrically connected to the gate structure by a lateral extension of the conductive layer outside of the anode trench.

5 . The method of claim 1 , further comprising:
forming a macro-cell that includes a plurality of the at least one PN diode power devices; and forming a plurality of the macro-cells for the semiconductor structure connected together to operate as a single PN diode power device.

6 . The method of claim 1 , further comprising:
forming a plurality of like PN diode power devices for the at least one PN diode power device; wherein: the plurality of like PN diode power devices are connected together through a bus structure to operate as a single PN diode power device the method is part of a chip-scale assembly; and the chip-scale assembly comprises a redistribution layer coupling the bus structure to anode and cathode external contacts.

7 . A method of forming a PN diode power device, comprising:
forming an active region; forming a buried well in the active region, the buried well having a first conductivity type; forming an anode terminal, the anode terminal making electrical contact with the buried well; forming a cathode region in the active region proximate an upper surface of the active region, the cathode region having a second conductivity type; forming a cathode terminal electrically connected to the cathode region; and forming an anode region in the active region proximate the upper surface of the active region, wherein the anode region has the first conductivity type, the anode region is formed over the buried well between the anode terminal and the cathode region, and the anode terminal is electrically connected to the anode region; wherein: the buried well has a first end below the anode terminal and a second end that extends partially below the cathode region, the second end being laterally spaced from the cathode terminal; the anode region forms a PN junction of the PN diode power device with the cathode region; and the buried well is configured, in conjunction with the cathode region, to form a clamping diode operative to position a breakdown avalanche region between the buried well and the cathode terminal, a breakdown voltage of the PN diode power device being a function of one or more characteristics of the buried well.

8 . The method of claim 7 , further comprising:
forming a gate structure above the active region proximate the upper surface of the active region; and electrically connecting the gate structure to the anode terminal; wherein: the gate structure overlaps the PN junction; and the gate structure is configured to control an electric field distribution proximate the PN junction.

9 . The method of claim 8 , wherein:
the gate structure is disposed over a portion of the anode region; the anode terminal is laterally spaced from the gate structure; and the anode region has a first end disposed proximate the anode terminal and a second end disposed underneath the gate structure at the PN junction.

10 . The method of claim 8 , further comprising:
forming a shielding structure proximate the upper surface of the active region between the gate structure and the cathode terminal, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate structure nearest the cathode terminal.

11 . The method of claim 7 , further comprising:
forming a highly doped implant region of the second conductivity type in the cathode region; wherein: the highly doped implant region makes electrical contact with the cathode terminal; and the highly doped implant region is laterally spaced from the PN junction.

12 . The method of claim 7 , further comprising:
forming an anode trench in the active region, wherein the anode terminal is disposed at least in part in the anode trench and electrically connected to the buried well and the anode region in the anode trench.

13 . The method of claim 12 , further comprising:
electrically connecting the anode trench to the buried well and the anode region with a conductive layer disposed along the anode trench.

14 . The method of claim 7 , wherein:
the buried well has a higher doping concentration than that of the anode region.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Korec Jacek
• Yang Boyi

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title