Semiconductor packaging

Patent metadata

Field	Value
Publication number	US-2023420438-A1
Application number	US-202217849300-A
Country	US
Kind code	A1
Filing date	Jun 24, 2022
Priority date	Jun 24, 2022
Publication date	Dec 28, 2023
Grant date	—

Abstract

The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

First claim

What is claimed is:

1 . A structure, comprising:
an adhesion layer in contact with a first semiconductor package; a first joint pad in contact with the adhesion layer; a film layer disposed on the first semiconductor package and the first joint pad, wherein:
the film layer comprises a slanted sidewall;
the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad; and
the slanted sidewall exposes a second portion of the first joint pad; and
a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

2 . The structure of claim 1 , wherein a thickness of the adhesion layer is between about 10 nm and about 1000 nm.

3 . The structure of claim 1 , wherein a thickness of the first joint pad is between about 0.5 μm and about 300 μm.

4 . The structure of claim 1 , wherein a ratio between a thickness of the first joint pad and a thickness of the adhesion layer is between about 10 and about 300.

5 . The structure of claim 1 , wherein a ratio between a width of the adhesion layer and a width of the second portion of the first joint pad is between about 1.2 and about 10.

6 . The structure of claim 1 , wherein an angle between the slanted sidewall and a horizontal direction is between about 30° and about 80°.

7 . The structure of claim 1 , further comprising:
a through-interposer via (TIV) structure disposed adjacent to the first semiconductor package and electrically coupling the first and second semiconductor packages; a molding layer between the first semiconductor package and the TIV structure; and a filling layer adjacent to the solder ball and between the film layer and the second semiconductor package.

8 . The structure of claim 1 , further comprising a first redistribution layer (RDL) and an input/output (I/O) connection disposed below the first semiconductor package, wherein the I/O connection is electrically coupled to one or more second RDLs disposed below the I/O connection.

9 . The structure of claim 1 , wherein the first semiconductor package comprises a system-on-a-chip (SOC) comprising one or more sensors, and wherein the second semiconductor package comprises one or more memory devices.

10 . The structure of claim 1 , further comprising a third semiconductor package disposed adjacent to the first semiconductor package and electrically coupled to the first and second semiconductor packages, wherein the third semiconductor package comprises a power management device.

11 . A structure, comprising:
a substrate comprising a first redistribution layer (RDL) and a first ball grid array (BGA); an input/output (I/O) connection disposed on and electrically coupled to the first RDL; a second RDL disposed on and electrically coupled to the I/O connection; a system-on-a-chip (SOC) disposed on and electrically coupled to the second RDL; a joint section comprising:
an adhesion layer in contact with the SOC;
a first joint pad in contact with the adhesion layer; and
a die attach film (DAF) disposed on the SOC and covering end portions of the adhesion layer and the first joint pad; and
a second BGA attached to the first joint pad and a second joint pad of a semiconductor package.

12 . The structure of claim 11 , wherein a ratio between a thickness of the first joint pad and a thickness of the adhesion layer is between about 10 and about 300.

13 . The structure of claim 11 , wherein the DAF exposes a middle portion of the first joint pad, and wherein a ratio between a width of the adhesion layer and a width of the middle portion of the first joint pad is between about 1.2 and about 10.

14 . The structure of claim 11 , wherein the DAF comprises a slanted sidewall, and wherein an angle between the slanted sidewall and a horizontal direction is between about 30° and about 80°.

15 . The structure of claim 11 , wherein the joint section further comprises a filling layer adjacent to the second BGA and between the DAF and the semiconductor package.

16 . The structure of claim 11 , further comprising an other semiconductor package disposed adjacent to the SOC and electrically coupled to the SOC and the semiconductor package.

17 . A method, comprising:
forming an adhesion layer in contact with a first semiconductor package; forming a first joint pad in contact with the adhesion layer; forming a film layer on the first semiconductor package and the first joint pad, comprising:
forming a slanted sidewall of the film layer;
covering an end portion of the adhesion layer and a first portion of the first joint pad; and
exposing a second portion of the first joint pad; and
forming a ball grid array (BGA) between the second portion of the first joint pad and a second joint pad of a second semiconductor package.

18 . The method of claim 17 , further comprising:
forming a through-interposer via (TIV) structure adjacent to the first semiconductor package; forming a first redistribution layer (RDL) and an input/output (I/O) connection below the first semiconductor package; and forming a second RDL below the I/O connection to electrically couple to the I/O connection and the TIV structure.

19 . The method of claim 18 , further comprising:
filling a space between the TIV structure and the first semiconductor package with a molding layer; and filling a space adjacent to the BGA and between the film layer and the second semiconductor package with a filling layer.

20 . The method of claim 17 , wherein exposing the second portion of the first joint pad comprises removing a portion of the film layer by a laser milling process, a dry etch process, or a wet etch process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tien-Chung
• Huang Li-Hsien
• Wu Ming-Feng
• Chuang Yao-Chun
• He Jun

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title