Semiconductor package

Patent metadata

Field	Value
Publication number	US-2021028137-A1
Application number	US-202016795733-A
Country	US
Kind code	A1
Filing date	Feb 20, 2020
Priority date	Jul 22, 2019
Publication date	Jan 28, 2021
Grant date	—

Abstract

Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

First claim

1 . A semiconductor package, comprising:
a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes:
an under-bump pattern;
a lower dielectric layer that covers a sidewall of the under-bump pattern; and
a first redistribution pattern on the lower dielectric layer, the first redistribution pattern including a first line part,
wherein a width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern, and wherein a thickness of the under-bump pattern is greater than a thickness of the first line part.

2 . The semiconductor package of claim 1 , wherein the first redistribution pattern further includes a first via part between the under-bump pattern and the first line part.

3 . The semiconductor package of claim 2 , wherein a width of the first via part is less than the width at the top surface of the under-bump pattern.

4 . The semiconductor package of claim 1 , wherein the thickness of the under-bump pattern is 2.5 to 10 times the thickness of the first line part.

5 . The semiconductor package of claim 1 , wherein the first redistribution pattern includes:
a first conductive layer on a top surface of the lower dielectric layer; and a first seed layer between the top surface of the lower dielectric layer and the first conductive layer, the first seed layer extending onto and contacting the top surface of the under-bump pattern.

6 . The semiconductor package of claim 1 ,
wherein the first line part includes a plurality of first line parts that are spaced apart from each other, and wherein a maximum interval between a bottom surface of the lower dielectric layer and bottom surfaces of the first line parts is 100% to 130% of a minimum interval between the bottom surface of the lower dielectric layer and the bottom surfaces of the first line parts.

7 . The semiconductor package of claim 1 , further comprising:
an upper dielectric layer on the lower dielectric layer; and a second redistribution pattern on a top surface of the upper dielectric layer, the second redistribution pattern including a second line part, wherein the thickness of the under-bump pattern is greater than a thickness of the second line part.

8 . The semiconductor package of claim 1 , further comprising an external terminal on the bottom surface of the under-bump pattern.

9 . The semiconductor package of claim 8 , further comprising:
a lower under-bump pattern between the under-bump pattern and the external terminal; and a seed pattern between the lower under-bump pattern and the under-bump pattern, wherein the lower under-bump pattern includes a material different from a material of the under-bump pattern.

10 . The semiconductor package of claim 1 , further comprising:
a connection substrate on the redistribution substrate, the connection substrate including a plurality of base layers and a conductive structure, wherein the connection substrate has a hole, and wherein the semiconductor chip is disposed in the hole.

11 . The semiconductor package of claim 1 , further comprising:
a conductive structure on the top surface of the redistribution substrate, the conductive structure being spaced apart from the semiconductor chip; and a molding layer on the top surface of the redistribution substrate, the molding layer encapsulating the semiconductor chip and a sidewall of the conductive structure.

12 . A semiconductor package, comprising:
a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer that covers a sidewall of the under-bump pattern; and
a redistribution pattern on the under-bump pattern, the redistribution pattern being coupled to the under-bump pattern,
wherein an angle between the sidewall and a bottom surface of the under-bump pattern is in a range from 105° to 135°.

13 . The semiconductor package of claim 12 , wherein the dielectric layer exposes the bottom surface of the under-bump pattern.

14 . The semiconductor package of claim 13 , wherein the bottom surface of the under-bump pattern is coplanar with a bottom surface of the dielectric layer.

15 . The semiconductor package of claim 12 ,
wherein the redistribution pattern includes a via part in contact with a top surface of the under-bump pattern, and wherein a width of the via part is less than a width of the under-bump pattern.

16 . The semiconductor package of claim 12 ,
wherein the dielectric layer has an opening that exposes a top surface of the under-bump pattern, wherein the redistribution pattern includes a seed layer, and wherein the seed layer covers a sidewall of the opening and the top surface of the under-bump pattern, the top surface of the under-bump pattern being exposed to the opening.

17 . A semiconductor package, comprising:
a redistribution substrate; and a semiconductor chip on a top surface of the redistribution substrate, wherein the redistribution substrate includes:
a conductive terminal pad;
a lower dielectric layer that covers a sidewall of the conductive terminal pad;
a line pattern on the lower dielectric layer; and
a via between the conductive terminal pad and the line pattern, the via being in contact with a top surface of the conductive terminal pad,
wherein a thickness of the conductive terminal pad is greater than a thickness of the line pattern, and wherein a width of the via is less than a width of the conductive terminal pad.

18 . The semiconductor package of claim 17 , wherein an angle between the sidewall and a bottom surface of the conductive terminal pad is in a range from 105° to 135°.

19 . The semiconductor package of claim 17 , wherein the thickness of the conductive terminal pad is 2.5 to 10 times the thickness of the line pattern.

20 . The semiconductor package of claim 17 ,
wherein the lower dielectric layer includes a first dielectric layer and a second dielectric layer that are stacked, wherein the via is provided in the second dielectric layer, and wherein the line pattern is provided on a top surface of the second dielectric layer and is connected to the via.

21 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Gwangjae
• Kim Dongkyu
• Park Jung-Ho
• Jang Yeonho

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title