Semiconductor package

Patent metadata

Field	Value
Publication number	US-2023420402-A1
Application number	US-202318244462-A
Country	US
Kind code	A1
Filing date	Sep 11, 2023
Priority date	Jul 22, 2019
Publication date	Dec 28, 2023
Grant date	—

Abstract

Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

First claim

1 .- 21 . (canceled)

22 . A method of manufacturing a semiconductor package comprising
forming a redistribution substrate; and placing a semiconductor chip on the redistribution substrate, wherein forming a redistribution substrate includes: forming a first seed layer on a carrier substrate; forming a first dielectric pattern including a first opening on the first seed layer; forming an under-bump pattern within the first opening; forming a second dielectric pattern including a second opening on the first dielectric pattern and the under-bump pattern, the second opening exposing a top surface of the under-bump pattern; sequentially forming a second seed layer and a conductive layer that fill the second opening and extend to the top surface of the second dielectric pattern; and forming a redistribution pattern by patterning the second seed layer and the conductive layer.

23 . The method of claim 22 , wherein the first dielectric pattern and the second dielectric pattern include the same dielectric material.

24 . The method of claim 22 , wherein the first dielectric pattern and the second dielectric pattern include a photodielectric polymer.

25 . The method of claim 22 , wherein forming the first dielectric pattern includes:
coating a first dielectric layer on the first seed layer; forming a first preliminary opening by performing an exposure and development process on the first dielectric layer; and forming a first opening by curing the first dielectric layer.

26 . The method of claim 22 , wherein forming the under-bump pattern includes performing an electroplating process using the first seed layer as an electrode.

27 . The method of claim 22 , wherein the under-bump pattern and the first seed layer include different metal materials, and the under-bump pattern is in direct contact with a sidewall of the first dielectric pattern exposed by the first opening.

28 . The method of claim 22 , wherein a level difference between the top surface of the under-bump pattern and the top surface of the first dielectric pattern is less than a thickness of the under-bump pattern.

29 . The method of claim 22 , further comprising disposing a release layer between the carrier substrate and the first seed layer before forming the first seed layer.

30 . The method of claim 29 , further comprising:
exposing the first seed layer by removing the carrier substrate and the release layer; and removing the first seed layer to expose a lower surface of the first dielectric pattern and a lower surface of the under-bump pattern.

31 . The method of claim 30 , further comprising directly forming an external connection terminal on the exposed lower surface of the under-bump pattern.

32 . The method of claim 29 , further comprising:
exposing the first seed layer by removing the carrier substrate and the release layer; forming a mask pattern including a third opening exposing the first seed layer on a lower surface of the first seed layer; forming a lower under-bump pattern within the third opening, wherein a metal material is different from the first seed layer and the under-bump pattern; removing the mask pattern; and forming a first seed pattern by patterning the first seed layer.

33 . The method of claim 22 , wherein the redistribution pattern includes a via portion and a wiring portion on the via portion, the via portion is formed within the second opening, the wiring portion is formed on the top surface of the second dielectric pattern and the via portion, and a thickness of the under-bump pattern is greater than a thickness of the wiring portion.

34 . The method of claim 33 , wherein the thickness of the under-bump pattern is 2.5 to 10 times the thickness of the wiring portion.

35 . A method of manufacturing a semiconductor package comprising:
forming a redistribution substrate; and placing a semiconductor chip on the redistribution substrate, wherein forming a redistribution substrate includes:
forming a first seed layer on a carrier substrate;
forming a first dielectric pattern including a first opening on the first seed layer;
forming an under-bump pattern within the first opening;
forming a second dielectric pattern including a second opening on the first dielectric pattern and the under-bump pattern, wherein the second opening exposes a top surface of the under-bump pattern; and
forming a redistribution pattern that fills the second opening and extends onto a top surface of the second dielectric pattern.

36 . The method of claim 35 , wherein the first seed layer is in contact with a bottom surface of the first dielectric pattern, and is spaced apart from a side surface of the first dielectric pattern.

37 . The method of claim 35 , wherein forming the redistribution pattern includes:
sequentially forming a second seed layer and a conductive layer that fill the second opening and extend to the top surface of the second dielectric pattern; and patterning the second seed layer and the conductive layer, wherein the redistribution pattern includes a via portion and a wiring portion on the via portion, the via portion is formed within the second opening, and the wiring portion is formed on the top surface of the second dielectric pattern and the via portion.

38 . The method of claim 37 , wherein the second seed layer is formed directly on the top surface of the under-bump pattern.

39 . The method of claim 35 ,
wherein the first seed layer and the under-bump pattern include different metal materials, and wherein the under-bump pattern is in direct contact with the first dielectric pattern.

40 . The method of claim 35 , wherein forming the first dielectric pattern includes:
coating a first dielectric layer including a photosensitive dielectric material on the first seed layer; forming a first preliminary opening by performing an exposure and development process on the first dielectric layer; and curing the first dielectric layer to form a first opening from the first preliminary opening.

41 . The method of claim 35 , wherein forming the under-bump pattern includes forming a vertical level of a top surface of the under-bump pattern to be less than or equal to a vertical level of a top surface of the first dielectric pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Gwangjae
• Kim Dongkyu
• Park Jung-Ho
• Jang Yeonho

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title