Semiconductor device and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-2020335441-A1
Application number	US-201916387924-A
Country	US
Kind code	A1
Filing date	Apr 18, 2019
Priority date	Apr 18, 2019
Publication date	Oct 22, 2020
Grant date	—

Abstract

In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.

First claim

1 . A semiconductor device, comprising:
a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material; an electronic device on the top surface of the RDL substrate; an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device; a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate; and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate.

2 . The semiconductor device of claim 1 , wherein the electrical interconnect comprises a conductive post on the bottom surface of the RDL substrate, a conductive pillar on the conductive post, and an interconnect tip on the conductive pillar.

3 . The semiconductor device of claim 2 , wherein the electrical interconnect further comprises a seed layer between the conductive post and the conductive pillar.

4 . The semiconductor device of claim 1 , wherein the electrical interconnect comprises an under bump metal on the bottom surface of the RDL substrate.

5 . The semiconductor device of claim 1 , wherein the electrical interconnect comprises a conductive post on the bottom surface of the RDL substrate and a solder ball on the conductive post.

6 . The semiconductor device of claim 1 , wherein the RDL substrate comprises a conductive layer and a dielectric layer.

7 . The semiconductor device of claim 6 , further comprising an additional electrical interconnect on the top surface of the RDL substrate to couple the electronic device to the electrical interconnect on the bottom surface of the RDL substrate via the conductive layer.

8 . The semiconductor device of claim 1 , wherein the first protective material and the second protective material comprise a same material having a same coefficient of thermal expansion (CTE).

9 . The semiconductor device of claim 1 , wherein the first protective material and the second protective material comprise different materials having a same or similar coefficient of thermal expansion (CTE).

10 . The semiconductor device of claim 1 , wherein the first protective material has a first coefficient of thermal expansion (CTE) and a first thickness and the second protective material has a second CTE and a second thickness such that warpage between the first protective material and the RDL substrate counters warpage between the second protective material and the RDL substrate.

11 . A method to manufacture a semiconductor device, comprising:
forming a base structure having a conductive post; forming a redistribution layer (RDL) substrate on the base structure; placing an electronic device on a top surface of the RDL substrate; and forming a protective material contacting a side surface of the electronic device and the top surface of the RDL substrate.

12 . The method of claim 11 , wherein the conductive post is formed using a plating operation and the base structure is formed using a molding operation after the plating operation.

13 . The method of claim 11 , wherein the RDL substrate comprises a filler-free dielectric material and the conductive post is formed using a plating operation, and further comprising forming a conductive pillar on the conductive post using a second plating operation and forming an interconnect tip on the conductive post using a third plating operation.

14 . The method of claim 11 , wherein forming the RDL substrate comprises:
forming a first dielectric layer on the base structure; forming an opening in the dielectric layer to expose the conductive post; and forming a conductive layer on the dielectric layer and the conductive post.

15 . The method of claim 11 , wherein the base structure is formed on a first carrier using a first molding operation and the protective material is formed using a second molding operation, and the method further comprising:
attaching a second carrier on the protective material; removing the first carrier; and de-attaching the second carrier after the removing of the first carrier.

16 . A method to manufacture a semiconductor device, comprising:
forming a redistribution layer (RDL) substrate on a first carrier, the RDL substrate having a top surface and a bottom surface; placing an electronic device on the top surface of the RDL substrate; forming a first protective material using a first molding operation, wherein the first protective material contacts a side surface of the electronic device and the top surface of the RDL substrate; attaching a second carrier to the first protective material; removing the first carrier from the RDL substrate; forming a conductive post on the bottom surface of the RDL substrate using a first plating operation; and forming a second protective material using a second molding operation, wherein the second protective material contacts a side surface of the conductive post and the bottom surface of the RDL substrate.

17 . The method of claim 16 , further comprising forming a conductive pillar on the conductive post using a second plating operation and forming an interconnect tip on the conductive post using a third plating operation.

18 . The method of claim 16 , further comprising forming a solder ball on the conductive post.

19 . The method of claim 17 , further comprising removing the second carrier after the third plating operation.

20 . The method of claim 16 , wherein the first carrier is removed using a grinding or etching operation.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Kim Tae Ki
• Shim Jae Beom
• Son Seung Nam
• Do Won Chul

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/07236

  Soldering or alloying · CPC title