Power semiconductor device

Patent metadata

Field	Value
Publication number	US-2023411514-A1
Application number	US-202318240304-A
Country	US
Kind code	A1
Filing date	Aug 30, 2023
Priority date	Mar 1, 2021
Publication date	Dec 21, 2023
Grant date	—

Abstract

In at least one embodiment, the power semiconductor device 1 ) involves a semiconductor body ( 2 ), at least one source region ( 21 ) in the semiconductor body ( 2 ), a gate electrode ( 3 ) at the semiconductor body ( 2 ), a gate insulator ( 4, 41, 42 ) between the semiconductor body ( 2 ) and the gate electrode ( 3 ), and at least one well region ( 22 ) at the at least one source region ( 21 ) and at the gate insulator ( 4, 41, 42 ), wherein the gate insulator ( 4, 41, 42 ) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator ( 4, 41, 42 ) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region ( 22 ) than in remaining regions of the gate insulator ( 4, 42 ).

First claim

What is claimed is:

1 . A power semiconductor device comprising:
a semiconductor body, at least one source region in the semiconductor body, a gate electrode at the semiconductor body, a gate insulator between the semiconductor body and the gate electrode, and at least one well region at the at least one source region and at the gate insulator, wherein the gate insulator has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator at a specific location thereof, the dielectric capacitance is larger at the at least one well region than in remaining regions of the gate insulator, and seen in cross-section, the gate insulator is composed of two first gate insulator regions having the larger dielectric capacitance and of a central, second gate insulator region having the smaller dielectric capacitance, the at least one well region is in direct contact only with the first gate insulator regions and not with the second gate insulator region.

2 . The power semiconductor device according to claim 1 , wherein at least one of:
the semiconductor body is of a wide bandgap material or of silicon carbide, and the power semiconductor device is a field-effect transistor or an insulated gate bipolar transistor.

3 . The power semiconductor device according to claim 1 ,
wherein the gate insulator comprises a first material and a second material, the second material has a higher relative dielectric constant than the first material, and wherein the second material is a continuous layer completely extending between the gate electrode and the semiconductor body.

4 . The power semiconductor device according to claim 1 ,
wherein the first material is located at a side of the second material remote from the semiconductor body, wherein the semiconductor body is in direct contact with the second material but not with the first material, and wherein the continuous layer of the second material has a constant geometric layer thickness.

5 . The power semiconductor device according to claim 3 ,
wherein the second material is located at a side of the first material remote from the semiconductor body so that both the first material and the second material are in direct contact with the semiconductor body.

6 . The power semiconductor device according to claim 3 ,
wherein the gate insulator is of constant geometric thickness and the first material and the second material are located next to one another in a common plane, and wherein the first material and the second material are in direct contact with the semiconductor body.

7 . The power semiconductor device according to claim 1 ,
wherein the gate insulator is of one material so that the gate insulator has a non-varying relative dielectric constant but a varying geometric thickness, and wherein the geometric thickness is largest in a central part of the gate insulator, seen in cross-section.

8 . The power semiconductor device according to claim 1 ,
wherein the gate electrode is of planar configuration so that the gate electrode is located on a top side of the semiconductor body and the top side is of planar fashion.

9 . The power semiconductor device according to claim 1 ,
wherein the gate electrode is of trench configuration so that the gate electrode extends into a trench of the semiconductor body, the gate electrode reaches deeper into the semiconductor body than the at least one well region, and the at least one well region directly adjoins the trench.

10 . The power semiconductor device according to claim 1 ,
wherein the first gate insulator regions are located at edges of the gate electrode and the second gate insulator region is located at a middle portion of the gate electrode.

11 . The power semiconductor device according to claim 1 ,
wherein the semiconductor body further comprises a drift region, wherein the drift region and the at least one source region are of a first conductivity type, and the at least one well region is of a second conductivity type different from the first conductivity type, wherein the only region of the semiconductor body, with which the second gate insulator region is in contact with, is the drift region, and wherein, seen in cross-section, the first gate insulator regions are in contact with the at least one source region and with the at least one well region as well as with the drift region.

12 . The power semiconductor device according to claim 1 ,
wherein a proportion of the second gate insulator region along an interface of the gate electrode facing the semiconductor body is between 20% and 80% inclusive of an overall extent of said interface, wherein, seen in cross-section, the first gate insulator regions are located along said interface symmetrically around the second gate insulator region.

13 . The power semiconductor device according to claim 1 ,
wherein the dielectric capacitance of the first gate insulator regions is at least 1.4 times and at most 6 times the dielectric capacitance of the second gate insulator region.

14 . The power semiconductor device according to claim 1 ,
wherein an overall geometric thickness of the gate insulator is between 10 nm and 1.5 μm inclusive.

15 . The power semiconductor device according to claim 1 , comprising at least two source regions and a source electrode which is in electric contact with the at least two of the source regions,
wherein, seen in cross-section,
the gate electrode is located between two of the at least two source regions,
the source electrode covers the gate electrode on a side remote from the semiconductor body so that the source electrode is a common electrode for the at least two source regions.

Assignees

• Hitachi Energy Switzerland Ag

Inventors

• Romano Gianpaolo
• Knoll Lars
• Arango Yulieth
• Wirths Stephan
• Mihaila Andrei

Classifications

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title