Interface layer control methods for semiconductor power devices and semiconductor devices formed thereof

Patent metadata

Field	Value
Publication number	US-2021336022-A1
Application number	US-202016855161-A
Country	US
Kind code	A1
Filing date	Apr 22, 2020
Priority date	Apr 22, 2020
Publication date	Oct 28, 2021
Grant date	—

Abstract

A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.

First claim

1 . A semiconductor device comprising:
a semiconductor layer structure; a gate insulating pattern on the semiconductor layer structure; a gate electrode on the gate insulating pattern; and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.

2 . The semiconductor device of claim 1 , wherein the first segment of the interface layer extends from an edge of the gate insulating pattern in a direction towards a center portion of the gate insulating pattern.

3 . The semiconductor device of claim 2 , wherein a dopant concentration of a portion of the first segment of the interface layer decreases as the first segment extends towards the center portion of the gate insulating pattern.

4 . The semiconductor device of claim 2 , wherein a thickness of the gate insulating pattern is greater near the edge of the gate insulating pattern than in the center portion of the gate insulating pattern.

5 . The semiconductor device of claim 1 , wherein the first segment and the second segment of the interface layer are substantially coplanar.

6 . The semiconductor device of claim 1 , wherein the semiconductor layer structure comprises a first source/drain region, a second source/drain region, and a junction field effect transistor (JFET) region between the first source/drain region and the second source/drain region.

7 . The semiconductor device of claim 6 , wherein the gap is over at least a portion of the JFET region.

8 . The semiconductor device of claim 1 , wherein the interface layer comprises hydrogen (H), nitrogen (N), boron (B), phosphorous (P), lanthanum (La), strontium (Sr), and/or barium (Ba).

9 . The semiconductor device of claim 1 , wherein the interface layer further comprises a third segment that is farther from a top surface of the semiconductor layer structure than the first segment or the second segment.

10 . The semiconductor device of claim 9 , further comprising a dielectric pattern between the top surface of the semiconductor layer structure and the third segment of the interface layer.

11 . The semiconductor device of claim 1 , wherein a portion of the gate electrode extends below a top surface of the semiconductor layer structure.

12 . A semiconductor device comprising:
a semiconductor layer structure comprising a first source/drain region, a second source/drain region, and a junction field effect transistor (JFET) region between the first source/drain region and the second source/drain region; a gate insulating pattern on the semiconductor layer structure; a gate electrode on the gate insulating pattern; and an interface layer comprising a first segment and a second segment, wherein the first segment is between the first source/drain region and the gate insulating pattern, wherein the second segment is between the second source/drain region and the gate insulating pattern, and wherein an upper surface of the semiconductor layer structure between at least a portion of the JFET region and the gate insulating pattern is free of the interface layer.

13 . The semiconductor device of claim 12 , wherein the first segment of the interface layer extends towards the JFET region from a first position over the first source/drain region to a second position beyond the first source/drain region that is between the gate insulating pattern and the upper surface of the semiconductor layer structure.

14 . The semiconductor device of claim 13 , wherein a dopant concentration of the first segment of the interface layer decreases as the first segment extends towards the second position.

15 . (canceled)

16 . The semiconductor device of claim 12 , wherein the interface layer further comprises a third segment on the JFET region that is farther from a top surface of the semiconductor layer structure than the first segment or the second segment.

17 . The semiconductor device of claim 16 , further comprising a dielectric pattern between the JFET region and the third segment of the interface layer.

18 . (canceled)

19 . A semiconductor device comprising:
a semiconductor layer structure; a gate insulating pattern on the semiconductor layer structure; a gate electrode on the gate insulating pattern; and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having first and second edge portions on opposite sides of a center portion, wherein a dopant concentration of the interface layer decreases from the first edge portion to the center portion.

20 . The semiconductor device of claim 19 , wherein a first segment of the interface layer extends from the first edge portion of the interface layer in a direction towards the center portion of the interface layer.

21 . The semiconductor device of claim 19 , wherein a change in the dopant concentration of the interface layer decreases from the first edge portion to the center portion is linear, exponential, step, and/or random.

22 . The semiconductor device of claim 19 , wherein the interface layer comprises a first segment in the first edge portion of the interface layer and a second segment in the second edge portion of the interface layer,
wherein the semiconductor layer structure comprises a first source/drain region, a second source/drain region, and a junction field effect transistor (JFET) region between the first source/drain region and the second source/drain region, and wherein the semiconductor device further comprises a gap between the first segment and the second segment of the interface layer that is over at least a portion of the JFET region.

23 . (canceled)

24 . The semiconductor device of claim 19 , wherein a portion of the gate electrode extends below a top surface of the semiconductor layer structure.

25 . The semiconductor device of claim 19 , wherein the interface layer is also present between the gate electrode and the gate insulating pattern.

26 - 41 . (canceled)

Assignees

• Cree Inc

Inventors

• Lichtenwalner Daniel Jenner

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/60

  Impurity distributions or concentrations · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title