Light absorbing layer to enhance p-type diffusion for dti in image sensors

Patent metadata

Field	Value
Publication number	US-2023411425-A1
Application number	US-202318364736-A
Country	US
Kind code	A1
Filing date	Aug 3, 2023
Priority date	May 13, 2021
Publication date	Dec 21, 2023
Grant date	—

Abstract

In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

First claim

1 - 14 . (canceled)

15 . An integrated chip (IC), comprising:
a substrate; a plurality of image sensing elements disposed in the substrate and comprising a first doping type; and a deep trench isolation (DTI) structure separating adjacent image sensing elements of the plurality of image sensing elements from one another and comprising:
an isolation filler structure disposed between sidewalls of the substrate;
a doped isolation layer disposed between the isolation filler structure and the substrate and comprising a second doping type opposite the first doping type, wherein the substrate is more heavily doped in a dopant diffusion region extending from the doped isolation layer into the substrate by a first distance; and
a light absorbing layer comprising a first material disposed between the isolation filler structure and the doped isolation layer, wherein the first material has an absorption coefficient of greater than approximately 10 4 centimeters −1 .

16 . The IC of claim 15 , wherein the light absorbing layer comprises germanium, titanium nitride, aluminum oxide, or a silicon-germanium alloy.

17 . The IC of claim 15 , wherein the first material extends from the DTI structure into the substrate by a second distance that is less than the first distance.

18 . The IC of claim 17 , wherein a concentration of the first material in the substrate is less than approximately 3 percent.

19 . The IC of claim 17 , wherein the second distance is greater than approximately 1 nanometer.

20 . The IC of claim 15 , wherein the first distance is greater than approximately 5 nanometers.

21 . An integrated chip (IC), comprising:
a substrate; a plurality of image sensing elements disposed in the substrate; and a deep trench isolation (DTI) structure separating adjacent image sensing elements of the plurality of image sensing elements from one another, the DTI structure comprising:
an isolation filler structure disposed within a trench, the trench defined by inner sidewalls of the substrate;
a doped isolation layer disposed between outer sidewalls of the isolation filler structure and the inner sidewalls of the substrate; and
a light absorbing layer disposed between the outer sidewalls the isolation filler structure and inner sidewalls of the doped isolation layer.

22 . The IC of claim 21 , wherein the image sensing elements comprise a first doping type, and the doped isolation layer comprises a second doping type opposite the first doping type, and wherein the substrate includes a dopant diffusion region extending from the doped isolation layer into the substrate by a first distance, the dopant diffusion region being more heavily doped than a base substrate region that is deeper into the substrate than the first distance.

23 . The IC of claim 21 , wherein the light absorbing layer has an absorption coefficient of greater than approximately 10 4 centimeters −1 .

24 . The IC of claim 21 , wherein an uppermost extent of the trench has a neck region with sidewalls that are spaced apart by a first distance and the trench has a body region with sidewalls that are spaced apart by a second distance that is greater than the first distance.

25 . The IC of claim 24 , wherein the isolation filler structure extends out of the trench above the neck region and over lateral surfaces of the substrate over the adjacent image sensing elements.

26 . The IC of claim 25 , wherein the light absorbing layer terminates at an uppermost extent of the neck region and does not extend over the lateral surfaces of the substrate.

27 . The IC of claim 21 , wherein the light absorbing layer comprises germanium, titanium nitride, aluminum oxide, or a silicon-germanium alloy.

28 . The IC of claim 21 , further comprising:
a high-k dielectric layer along sidewalls of the doped isolation layer.

29 . The IC of claim 21 , further comprising: an air gap in a central region of the trench, the air gap defined by inner sidewalls of the isolation filler structure.

30 . An integrated chip (IC), comprising:
a substrate comprising silicon; a plurality of image sensing elements disposed in the substrate, the plurality of image sensing elements comprising a first doping type; trenches disposed within the substrate between adjacent image sensing elements of the plurality of image sensing elements, the trenches defined by inner sidewalls of the substrate; an isolation filler structure disposed within a trench; a light absorbing layer disposed within the trench along outer sidewalls of the isolation filler structure; a diffusion enhancement layer disposed within the trench along outer sidewalls of the light absorbing layer; an insulating layer disposed within the trench along outer sidewalls of the diffusion enhancement layer; and doped isolation layer disposed within the trench along outer sidewalls of the insulating layer.

31 . The IC of claim 30 , further comprising:
a high-k dielectric layer in the trench along outer sidewalls of the doped isolation layer.

32 . The IC of claim 30 , wherein the isolation filler structure extends out of the trench and over lateral surfaces of the substrate over the adjacent image sensing elements.

33 . The IC of claim 32 , wherein the light absorbing layer terminates at an uppermost extent of the trench and does not extend over the lateral surfaces of the substrate.

34 . The IC of claim 30 , wherein the insulating layer has a thickness of approximately 1 nanometer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Yu-Hung
• Li Ching I
• Fang Yu-Siang
• Hsia Yu-Yao
• Tsai Min-Ying

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title