Semiconductor memory devices and electronic systems

Patent metadata

Field	Value
Publication number	US-2023403854-A1
Application number	US-202318180437-A
Country	US
Kind code	A1
Filing date	Mar 8, 2023
Priority date	Jun 14, 2022
Publication date	Dec 14, 2023
Grant date	—

Abstract

According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.

First claim

1 . A semiconductor memory device comprising:
a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including:
a plate disposed on the second face of the semiconductor layer, and
a plug extending from the plate through the semiconductor layer;
a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one another; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.

2 . The semiconductor memory device of claim 1 , wherein a width of the plug increases as the plug extends in a direction from the second face of the semiconductor layer toward the first face of the semiconductor layer.

3 . The semiconductor memory device of claim 1 , wherein the plug includes a first plug and a second plug spaced apart from each other along a direction parallel to the first face of the semiconductor layer, and
wherein the channel structure includes a first channel structure disposed on the first plug, and a second channel structure disposed on the second plug.

4 . The semiconductor memory device of claim 1 , wherein the channel structure includes a first channel structure and a second channel structure disposed on the plug, and spaced apart from each other along a direction parallel to the first face of the semiconductor layer.

5 . The semiconductor memory device of claim 1 , wherein a top face of the channel structure in the first direction is disposed in the plug.

6 . The semiconductor memory device of claim 1 , wherein the device further comprises a word-line cutting structure that extends through the plurality of gate electrodes and cuts the plurality of gate electrodes, and
wherein a top face of the word-line cutting structure in the first direction is disposed in the semiconductor layer.

7 . The semiconductor memory device of claim 6 , wherein the top face of the word-line cutting structure in the first direction is closer to the second face of the semiconductor layer than a top face of the channel structure in the first direction.

8 . The semiconductor memory device of claim 6 , wherein the word-line cutting structure is spaced apart from the source structure along a direction parallel to the first face of the semiconductor layer.

9 . The semiconductor memory device of claim 1 , wherein the device further comprises a cell contact that extends through the plurality of gate electrodes and that is electrically connected to at least one of the plurality of gate electrodes, and
wherein a top face of the cell contact in the first direction is disposed in the semiconductor layer.

10 . The semiconductor memory device of claim 9 , wherein the top face of the cell contact in the first direction is closer to the second face of the semiconductor layer than a top face of the channel structure in the first direction.

11 . The semiconductor memory device of claim 9 , wherein the cell contact is spaced apart from the source structure along a direction parallel to the first face of the semiconductor layer.

12 . The semiconductor memory device of claim 1 , wherein the device further comprises a source contact that extends through the plurality of gate electrodes and that is electrically connected to the source structure.

13 . The semiconductor memory device of claim 12 , wherein a top face of the source contact in the first direction is disposed in the plug.

14 . The semiconductor memory device of claim 1 , wherein a gate electrode closest to the first face of the semiconductor layer among the plurality of gate electrodes includes a third face facing the first face, and
wherein the third face of the gate electrode is closer to the first face of the semiconductor layer than a bottommost face of the plug in the first direction.

15 . The semiconductor memory device of claim 1 , wherein the channel structure includes a portion, wherein a width of the portion decreases as the portion extends in a direction from the first face to the second face of the semiconductor layer.

16 .- 23 . (canceled)

24 . A semiconductor memory device comprising:
a peripheral circuit structure; and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes:
a semiconductor layer including a first face facing the peripheral circuit structure and a second face opposite to the first face in a first direction directed upward from the first face to the second face;
a source structure including:
a plate disposed on the second face of the semiconductor layer; and
a plug extending from the plate through the semiconductor layer;

a mold structure disposed on the first face of the semiconductor layer, the mold structure including a plurality of gate electrodes sequentially stacked on one another;
a channel structure that extends through the plurality of gate electrodes, and that is electrically connected to the source structure;
a bit-line disposed between the peripheral circuit structure and the mold structure, and electrically connected to the channel structure;
a plurality of cell contacts disposed on the mold structure, wherein each of the plurality of cell contacts is electrically connected to at least one of the plurality of gate electrodes;
a word-line cutting structure that extends through the mold structure and cuts the plurality of gate electrodes; and
a dummy channel structure extending through the mold structure,
wherein each of the mold structure, the plurality of cell contacts, and the word-line cutting structure is spaced apart from the plate of the source structure via the semiconductor layer along a direction parallel to the first face of the semiconductor layer, and wherein the channel structure is disposed on the plug.

25 . (canceled)

26 . The semiconductor memory device of claim 24 , wherein, in the first direction, a vertical level of a top face of the channel structure is different from a vertical level of each of a top face of each of the plurality of cell contacts, a top face of the word-line cutting structure, and a top face of the dummy channel structure.

27 . (canceled)

28 . An electronic system comprising:
a main substrate; a semiconductor memory device disposed on the main substrate, wherein the semiconductor memory device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure; and a controller disposed on the main substrate and electrically connected to the semiconductor memory device, wherein the cell structure includes:
a base layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face;
a source structure including a plug extending through the base layer,
a plurality of gate electrodes disposed on the first face of the base layer and sequentially stacked on top of one another;
a channel structure disposed on the plug and extending through the plurality of gate electrodes, wherein the channel structure is electrically connected to the source structure;
a dummy channel structure disposed on the base layer and extending through the plurality of gate electrodes; and
a word-line cutting structure that is disposed on the base layer and that cuts the plurality of gate electrode

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji Young
• Kim Do Hyung
• Kim Ji Won
• Sung Suk Kang

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/50 Primary

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title