Interposers for memory device testing and characterization, including interposers for testing and characterizing decision feedback equalization circuitry of ddr5 memory devices

Patent metadata

Field	Value
Publication number	US-2023386596-A1
Application number	US-202318109830-A
Country	US
Kind code	A1
Filing date	Feb 14, 2023
Priority date	May 31, 2022
Publication date	Nov 30, 2023
Grant date	—

Abstract

Interposers for use in testing and characterizing memory devices, such as memory devices including decision feedback equalization circuitry, are disclosed herein. In one embodiment, an apparatus includes an interposer having a first interface couplable to a memory device, a second interface couplable to one or more testers, and a channel circuit between the first interface and the second interface. The channel circuit is configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.

First claim

What is claimed is:

1 . An apparatus, comprising:
an interposer comprising:
a first interface couplable to a memory device,
a second interface couplable to one or more testers, and
a channel circuit between the first interface and the second interface, the channel circuit configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.

2 . The apparatus of claim 1 , wherein:
the channel circuit includes a pair of electrical contacts; and the pair of electrical contacts is configured to receive a resistive element of the one or more resistive elements such that electrical contacts of the pair are coupled to one another.

3 . The apparatus of claim 1 , wherein the one or more resistive elements includes a resistor configured to function as a damping resistor at least when (a) the resistor is coupled to the first interface and the second interface of the interposer and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

4 . The apparatus of claim 1 , wherein the one or more resistive elements includes a resistor configured to simulate an on-die termination value of an additional memory device connected to the channel circuit at least when (a) the resistor is coupled to the first interface and the second interface of the interposer and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

5 . The apparatus of claim 1 , wherein the one or more resistive elements includes a capacitor configured to simulate an input/output (I/O) capacitance of an additional memory device connected to the channel circuit at least when (a) the capacitor is coupled to the first interface and the second interface of the interposer and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

6 . The apparatus of claim 1 , wherein:
the channel circuit includes a stub; and the stub is configured to generate reflections on the channel circuit at least when (a) the stub is coupled, via a resistive element of the one or more resistive elements, to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

7 . The apparatus of claim 1 , wherein:
the channel circuit includes a stub having a first portion and a second portion; the second portion is couplable to the first portion via a resistive element of the one or more resistive elements to increase a length of an operable portion of the stub; and the operable portion of the stub is configured to generate reflections on the channel circuit at least when (a) the operable portion of the stub is coupled to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

8 . The apparatus of claim 1 , wherein:
the channel circuit includes a first stub and a second stub; the first stub extends in a first direction along the interposer; the second stub extends in a second direction along the interposer different from the first direction; the first stub is configured to generate reflections on the channel circuit along the first direction at least when (a) the first stub is coupled, via a first resistive element of the one or more resistive elements, to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit; and the second stub is configured to generate reflections on the channel circuit along the second direction at least when (a) the second stub is coupled, via a second resistive element of the one or more resistive elements, to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

9 . The apparatus of claim 1 , wherein:
the channel circuit includes a low pass channel and a high pass channel; the signal is transmitted, via the low pass channel, between the first interface and the second interface at least when the first interface and the second interface are coupled to one another via a first resistive element of the one or more resistive elements and the low pass channel; and the signal is transmitted, via the high pass channel, between the first interface and the second interface at least when the first interface and the second interface are coupled to one another via a second resistive element of the one or more resistive elements and the high pass channel.

10 . The apparatus of claim 1 , wherein the channel circuit includes a first circuit portion configured to simulate an additional memory device connected to the channel circuit at least when (a) the first circuit portion is coupled, via a resistive element of the one or more resistive elements, to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

11 . The apparatus of claim 10 , wherein the first circuit portion simulates a clamshell arrangement of a dual in-line memory module (DIMM) and is positioned, at least in part, in or on a side of the interposer opposite the memory device at least when the memory device is coupled to the first interface.

12 . The apparatus of claim 10 , wherein the channel circuit further includes a second circuit portion different from the first circuit portion, wherein the second circuit portion is configured to simulate multiple additional memory devices connected to the channel circuit at least when (a) the second circuit portion is coupled, via a second resistive element of the one or more resistive elements, to the first interface and the second interface and (b) the signal is transmitted between the first interface and the second interface via the channel circuit.

13 . The apparatus of claim 12 , wherein the second circuit portion simulates a clamshell arrangement of a dual in-line memory module (DIMM) and is positioned, at least in part, in or on (a) a first side of the interposer and (b) a second side of the interposer opposite the first side.

14 . The apparatus of claim 1 , wherein the first interface includes a socket configured to receive and couple the memory device to the channel circuit.

15 . The apparatus of claim 1 , wherein, to change the measurable value of the signal, the channel circuit is configurable, via the one or more resistive elements, to generate inter-symbol interference (ISI) at the first interface for testing decision feedback equalization (DFE) circuitry of the memory device at least when the memory device is coupled to the first interface.

16 . A system, comprising:
a motherboard coupled to a tester for testing or characterizing a memory device; and an interposer including a first interface coupled to the memory device, a second interface coupled to the motherboard, and a channel circuit coupling the first interface to the second interface such that the memory device is coupled to the tester via the motherboard, wherein the channel circuit is configurable, via one or more resistive elements, to alter a measurable value of a signal transmitted between the tester and the memory device.

17 . The system of claim 16 , wherein:
the channel circuit includes at least one pair of electrical contacts configured to receive a resistive element of

Assignees

• Micron Technology Inc

Inventors

• Stave Eric J
• Acosta Luis Nathan Perez
• Gardiner Bryce A

Classifications

• G11C29/14 Primary

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C29/56016 Primary

  Apparatus features · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C29/50008

  of impedance · CPC title